Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
December 3, 2002
Interfacing an External Processor to the SL811HS/S
Introduction
The SL811HS is a dual-role capable, i.e., host or peripheral,
embedded USB controller. As such, it is designed to be easily
connected to a variety of external embedded processors
ranging from an 8051 to a StrongARM as a memory mapped
peripheral. The signal descriptions and transaction methods
described here equally apply to the SL811S peripheral only
device. This application note describes the typical methods
used to connect the SL811HS/S to an embedded processor.
Example circuits and signal descriptions are provided that
should help you become more confident that your design will
work the first time around.
This application note also describes a typical configuration of
support circuitry needed when a USB controller is incorporat-
ed into a USB-enabled embedded system. Two configura-
tions are demonstrated including host-only and peripheral-
only.
Signal Basics
The SL811HS/S incorporates an industry-standard ad-
dress/data bus. The requirements of the embedded proces-
sor signals are laid out in the following list.
• Active LOW CHIP SELECT signal
• Active LOW READ signal
• Active LOW WRITE signal
• Active HIGH INTERRUPT signal
• Address bus or GPIO
• Data bus, at least 8-bits wide
• GPIO to drive various signals such as RESET, USB bus
power enable, various resistors…etc. The number of GPIO
required is dependent on the controller’s configuration.
See the schematics later in this document for more infor-
mation.
CHIP SELECT (nCS) – nCS is used to enable the
SL811HS/S interface and read or write the SL811HS/S regis-
ters/memory. nCS essentially signals that the transaction is
intended for “this chip” as opposed to another one that might
share the same read or write signals. nCS must be asserted
by the embedded processor for at least 65 ns during a trans-
action in order for the transaction to be valid. With some em-
bedded processors this may require that the firmware set an
additional number of wait-states so that nCS does not cycle
too fast. Wait-state generation is processor dependent, so no
information will be given here on how to set additional wait
states. If the SL811HS/S is the only IC on the embedded pro-
cessor’s data bus, nCS can be continuously asserted.
READ (nRD) – nRD is an active LOW signal driven by the
embedded processor that is used to signal a register or mem-
ory read. Before a read can take place, the desired address
to read must be written into the SL811HS/S. During a read
nCS must also be asserted in order for the SL811HS/S to
recognize the assertion of nRD. The minimum pulse width of
the nRD pulse is 65 ns. 65 ns after the assertion of nRD the
D[7:0] signals switch from hi-z to driving mode and drive the
data bus until 5 ns after nRD is deasserted. The minimum
spacing in between nRD assertions is 85 ns.
WRITE (nWR) – nWR is an active LOW signal driven by the
embedded processor that is used to write an address, regis-
ter, or memory location. In conjunction with nWR, nCS must
also be asserted in order for the SL811HS/S to recognize the
assertion of the nWR signal. nWR is asserted LOW for a min-
imum of 65 ns. Data is written from the embedded processor
to the SL811HS/S on the rising edge of nWR. The data must
remain valid on the bus for 5 ns after nWR is deasserted in
order for it to be properly latched by the SL811HS/S. The
minimum spacing between nWR assertions is 85 ns.
ADDRESS (A0) – The A0 signal is driven by the embedded
processor and is used in conjunction with the nWR signal to
define a write as an address pointer or data. If A0 is LOW
during a write, the write goes to an address pointer register.
If A0 is HIGH, the write goes to a register or memory location
pointed to by the address pointer register. For instance, if we
want to write to the register at address 00h we would first
perform a write with D[7:0] set to 00h and A0 set LOW. Then
we would perform another write with D[7:0] set to the register
value and A0 set HIGH. The value of A0 must be held for
10 ns after the assertion of nWR in order for the write to be
properly recognized. Typically this signal would be connect-
ed to address bit 0 on an 8-bit processor, address bit 1 on a
16-bit processor, or address bit 2 on a 32-bit processor.
In some cases the embedded processor may be using an
older Intel
®
-type bus with multiplexed address and data pins,
and will typically have an address latch enable (ALE) signal.
If this is the case, an external flip-flop will be required to latch
the value of the A0 pin on the ALE edge (edge may depend
on the particular processor) as shown in Figure 1.
INTERRUPT (INTRQ) – The interrupt signal is asserted
HIGH by the SL811HS/S during a programmable interrupt
event. Some examples may include the completion of a trans-
action or the connection of a new peripheral device. INTRQ
is asserted HIGH until the interrupt event is cleared by writing
to the associated interrupt clearing register in the
SL811HS/S. The interrupt polarity is not programmable, so an
D Q
CLK
Addr/Data0
ALE
A0
Figure 1. Using ALE on a Multiplexed Bus
(21 Seiten)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern