Cypress Semiconductor CY7C1383D Bedienungsanleitung

18-Mbit (512K x 36/1M x 18) Flow-Through SRAMCY7C1381DCY7C1383DCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 •

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 10 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1381D/CY7C1383D incorporates a serial bound

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 11 of 29TAP Controller Block DiagramPerforming a TAP ResetA RESET is performed by forcing TMS HIGH

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 12 of 29The user must be aware that the TAP controller clock can onlyoperate at a frequency up to

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 13 of 29 3.3V TAP AC Test ConditionsInput pulse levels...

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 14 of 29 Notes: 11.All voltages referenced to VSS (GND).12.Bit #24 is “1” in the Register Definiti

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 15 of 29 Identification CodesInstruction Code DescriptionEXTEST 000 Captures I/O ring contents. Pl

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 16 of 29119-Ball BGA Boundary Scan Order[13, 14]CY7C1381D (256K × 36) CY7C1383D (512K × 18)Bit# Ba

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 17 of 29165-Ball BGA Boundary Scan Order[13, 15]CY7C1381D (256K x 36) CY7C1381D (256Kx36)Bit# Bal

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 18 of 29165-Ball BGA Boundary Scan Order[13, 15]CY7C1383D (512K x 18) CY7C1383D (512Kx18)Bit# Bal

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 19 of 29Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tes

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 2 of 29 1ADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFFERSINPUTREGIS

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 20 of 29 Thermal Resistance[18]Parameter Description Test Conditions100 TQFP Package119 BGA Packag

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 21 of 29Switching Characteristics Over the Operating Range[23, 24]Parameter Description133 MHz 100

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 22 of 29Timing DiagramsRead Cycle Timing[25]Note: 25.On this diagram, when CE is LOW: CE1 is LOW,

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 23 of 29 Write Cycle Timing[25, 26]Note: 26.Full width write can be initiated by either GW LOW; or

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 24 of 29Read/Write Cycle Timing[25, 27, 28]Notes: 27.The data bus (Q) remains in high-Z following

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 25 of 29ZZ Mode Timing [29, 30]Timing Diagrams (continued)tZZISUPPLYCLKZZtZZRECALL INPUTS(except Z

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 26 of 29Package Diagrams DIMENSIONS ARE IN MILLIMETERS.0.30±0.080.6520.00±0.1022.00±0.201.40±0.05

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 27 of 29Package Diagrams (continued)51-85115-*B119-Lead PBGA (14 x 22 x 2.4 mm) BG119

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 28 of 29© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 29 of 29Document History PageDocument Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flo

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 3 of 29Pin ConfigurationsAAAAA1A0NCNCVSSVDDAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQVDDQDQBDQBVSS

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/144MDQPCDQCDQDDQCDQDAA

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 5 of 29Pin Configurations (continued)165-ball fBGA (3 Chip Enable)CY7C1381D (512K x 36)234 5671ABC

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 6 of 29Pin DefinitionsName I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 7 of 29Functional OverviewAll synchronous inputs pass through input registers controlledby the ris

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 8 of 29order. Leaving MODE unconnected will cause the device todefault to a interleaved burst sequ

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *C Page 9 of 29Write Cycle, Begin Burst External L H L L H L X L X L-H DRead Cycle, Begin Burst External L