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Migrating From EZ-USB FX2™ to EZ-USB FX2LP™

www.cypress.com Document No. 001-42079 Rev. *D 6

this workaround, the wMaxPacketSize that could be

defined in the isochronous endpoint descriptor is limited to

1024 bytes.

Feature Enhancements

This section is for designers already familiar with the FX2

architecture who are creating a new application using

FX2LP This section highlights additional (along with the

essential and application based changes mention in the

prior two sections) improvements and changes in FX2LP.

An overview of the feature changes/additions in the

FX2LP are listed as follows:



Lower power



Enabling pull-up on D+



FIFO address lines hold time for asynchronous write



ECC generation on GPIF data



Additional Package with more GPIOs

(CY7C68015A/16A).

Lower Power

As far as the power source is concerned, the FX2LP uses

a different process than the FX2. The FX2LP uses an

internal 1.8 V regulator. The major result of this change is

to reduce the power consumption of the chip. The lower

current is obtained just by using the FX2LP with the

required crystal modifications. This configuration meets all

USB bus powered requirements of unconfigured current

(100 mA) and suspend current (500 A).

As a result of this lower power, to meet the unconfigured

current limit, it is no longer necessary to use the double

enumeration procedure where the device first enumerates

in full-speed with a current draw below 100 mA and then

disconnects and reconnects as a high-speed device. If an

existing design uses this procedure the designer can

remove the procedure in design. For new designs using

FX2LP, there is no concern as the part does meet the

100-mA limitation requirement for unconfigured current

while operating in either full or high speed.

Enabling Pull-up on D+

There is a minor difference with respect to when the

internal logic enables the pull-up on D+ to signal an attach

event to the host. In the case of the FX2, the pull-up on D+

is enabled on power-up. In the case of the FX2LP, the

pull-up on D+ is enabled when the reset is released (in a

deasserted state).

On plug-in, the FX2 enables the pull-up on D+ signaling at

attach event to the host. If the reset is held active for

longer than 100 ms, an attach signal is sent to the host

and the host begins its enumeration sequence (after 100

ms from when the attach is detected), while the FX2 is still

held in reset. Section 7.1.7.3 (page 150) of the USB 2.0

specification, provides further information on the debounce

interval (delta t3). While using the FX2 Cypress

recommends that a reset time of 10 ms with an RC

network of 100K/0.1 F be used.

The FX2LP has a more flexible reset timing requirement.

As the FX2LP enables the pull-up on the D+ after the

RESET is deasserted, there really is no restriction on the

reset timing as only the host receives an attach signal

when the RESET is released.

FIFO Address Lines Hold Time for

Asynchronous Write

In the case of an FX2 device, when operating in slave

FIFO mode in an asynchronous interface, the minimum

hold time (t

FAH

) for FIFO address lines (FIFOADR[1:0]) for

a slave FIFO write operation is 70 ns, that is measured

from the deasserting edge of SLWR.

This has been improved and optimized to 10 ns when

using the FX2LP parts. The FIFOADDR[1:0] lines hold

time (t

FAH

) for a slave FIFO asynchronous write is speed

for a minimum of 10 ns for the FX2LP.

ECC Generation on GPIF data

This is a new feature and does not affect existing designs.

If ECC generation is to be added to an existing design

there are additional registers that enable this function.

The FX2LP can be configured to either calculate two

separate 256-byte ECCs on two consecutive 256-byte

blocks of data, or alternatively one single 512-byte ECC

on a 512-byte block of data. After the 8051 resets the ECC

calculation by writing any value to ECCRESET, the FX2LP

calculates ECC on any data bytes that transfer across the

GPIF or Slave FIFO interface. The FX2LP stops ECC

calculation after all 512 bytes have been processed and it

waits for a new ECC reset from the 8051 before it

commences any new calculations.

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