Cypress Semiconductor CY7C1380C Bedienungsanleitung Seite 18
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PRELIMINARY
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B Page 18 of 28
Capacitance
[13]
Parameter Description Test Conditions
Max.
Unit100-TQFP 119-BGA 165-FBGA
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz TBD TBD TBD pF
C
CLK
Clock Input Capacitance TBD TBD TBD pF
C
I/O
Input/Output Capacitance TBD TBD TBD pF
AC Test Loads and Waveforms
[14]
Thermal Resistance
[13]
Parameter Description Test Conditions TQFP 119 BGA 165 FBGA Unit
Θ
JA
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 x 4.5
inch
2
, two-layer printed circuit
board
31 45 46 °C/W
Θ
JC
Thermal Resistance (Junction to Case) 6 7 3 °C/W
OUTPUT
R = 317/1667Ω
R = 351/1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
V
t
= 1.5 for 3.3V V
DDQ
3.3/2.5V
ALL INPUT PULSES
[14]
V
CC
GND
90%
10%
90%
10%
<
1ns
<
1ns
(c)
1.25V for 2.5V V
DDQ
OUTPUT
R
t
= 50Ω
Z
0
= 50Ω
30 pF
V
t
- Termination Voltage
R
t
- Termination Resistance
Switching Characteristics Over the Operating Range
[15, 16, 17]
Parameter Description
-250 -225 -200 -167 -133
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
CYC
Clock Cycle Time 4.0 4.4 5 6 7.5 ns
t
CH
Clock HIGH 1.7 2.0 2.0 2.2 2.5 ns
t
CL
Clock LOW 1.7 2.0 2.0 2.2 2.5 ns
t
AS
Address Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
t
AH
Address Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
t
CO
Data Output Valid After CLK Rise 2.6 2.8 3.0 3.4 4.2 ns
t
DOH
Data Output Hold After CLK Rise 1.0 1.0 1.3 1.3 1.3 ns
t
ADS
ADSP, ADSC Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
t
ADH
ADSP, ADSC Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
t
WES
BWE, GW, BW
x
Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
t
WEH
BWE, GW, BW
x
Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
t
ADVS
ADV Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
t
ADVH
ADV Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
t
DS
Data Input Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
t
DH
Data Input Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
t
CES
Chip enable Set-up 1.2 1.4 1.4 1.5 1.5 ns
t
CEH
Chip enable Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
Shaded areas contain advance information.
Notes:
13. Tested initially and after any design or process changes that may affect these parameters.
14. Input waveform should have a slew rate of
< 1 ns.
15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5/1.25V, input pulse levels of 0 to 3.0/2.5V
for 3.3/2.5V V
DDQ
respectively, and output loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
17. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
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