Cypress Semiconductor CY7C1380C Bedienungsanleitung Seite 15

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PRELIMINARY
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B Page 15 of 28
Identification Register Definitions
Instruction Field 512K x 36 1M x 18 Description
Revision Number (31:28) 0100 0100 Reserved for version number.
Cypress Device ID (27:24) 1010 1010 Reserved for internal use.
Device Type (23:18) 000000 000000 Defines memory type and architecture
Device Width and Density (17:12) 100101 010101 Defines width and density.
Cypress JEDEC ID (11:0) 000001101001 000001101001 Allows unique identification of SRAM vendor.
Scan Register Sizes
Register Name Bit Size (x18) Bit Size (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan 51 70
Identification Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Order (512K × 36) 119 BGA
Bit #
Signal
Name
Bump
ID Bit #
Signal
Name Bump ID
1 TBD TBD 36 TBD TBD
2 TBD TBD 37 TBD TBD
3 TBD TBD 38 TBD TBD
4 TBD TBD 39 TBD TBD
5 TBD TBD 40 TBD TBD
6 TBD TBD 41 TBD TBD
7 TBD TBD 42 TBD TBD
8 TBD TBD 43 TBD TBD
9 TBD TBD 44 TBD TBD
10 TBD TBD 45 TBD TBD
11 TBD TBD 46 TBD TBD
12 TBD TBD 47 TBD TBD
13 TBD TBD 48 TBD TBD
14 TBD TBD 49 TBD TBD
15 TBD TBD 50 TBD TBD
16 TBD TBD 51 TBD TBD
17 TBD TBD 52 TBD TBD
18 TBD TBD 53 TBD TBD
19 TBD TBD 54 TBD TBD
20 TBD TBD 55 TBD TBD
21 TBD TBD 56 TBD TBD
22 TBD TBD 57 TBD TBD
23 TBD TBD 58 TBD TBD
24 TBD TBD 59 TBD TBD
25 TBD TBD 60 TBD TBD
26 TBD TBD 61 TBD TBD
27 TBD TBD 62 TBD TBD
28 TBD TBD 63 TBD TBD
Boundary Scan Order (512K × 36) 119 BGA
Bit #
Signal
Name
Bump
ID Bit #
Signal
Name Bump ID
Seitenansicht 14
1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 27 28

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