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Document #: 38-08022 Rev. *C Page 31 of 49
Bit [7:0]: P0 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
Bit [7:0]: P1 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers. Figure 21-6 and Figure 21-7 control the interrupt
polarity of each GPIO pin.
Bit [7:0]: P0[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Figure 21-3. Interrupt Controller Logic Block Diagram
CLR
Global
Interrupt
Interrupt
Acknowledge
IRQout
USB-PS/2 Clear
Interrupt
Interrupt
Priority
Encoder
Enable [0]
D
Q
1
Enable
Bit
CLR
USB-PS/2 IRQ
128-µs CLR
128-µs IRQ
1-ms CLR
1-ms IRQ
EP0 IRQ
EP0 CLR
Wake-up IRQ
Vector
Enable [7]
CLK
CLR
D
Q
CLK
1
Wake-up CLR
Int
Wake-up
Int
USB-
EP1 IRQ
EP1 CLR
IRQ Pending
IRQ
Controlled by DI, EI, and
RETI Instructions
To CPU
CPU
PS/2
GPIO IRQ
GPIO CLR
EP2 IRQ
EP2 CLR
Capture A IRQ
Capture A CLR
Capture B IRQ
Capture B CLR
(Reg 0x20)
(Reg 0x20)
CLR
Enable [2]
D
Q
1
CLK
Int
EP2
(Reg 0x21)
Int Enable
Sense
(Bit 7, Reg 0xFF)
(Bit 2, Reg 0xFF)
SPI IRQ
SPI CLR
Bit # 76543210
Bit Name P0 Interrupt Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 21-4. Port 0 Interrupt Enable Register (Address
0x04)
Bit # 76543210
Bit Name P1 Interrupt Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 21-5. Port 1 Interrupt Enable Register
(Address 0x05)
Bit # 76543210
Bit Name P0 Interrupt Polarity
Read/Write WWWWWWWW
Reset 00000000
Figure 21-6. Port 0 Interrupt Polarity Register
(Address 0x06)
Bit # 76543210
Bit Name P1 Interrupt Polarity
Read/Write WWWWWWWW
Reset 00000000
Figure 21-7. Port 1 Interrupt Polarity Register
(Address 0x07)
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