Cypress Semiconductor CY7C0430CV Bedienungsanleitung

10 Gb/s 3.3V QuadPort™ DSE FamilyCY7C0430BVCY7C0430CVCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 10 of 37 Switching Characteristics Over the Industrial Operating Range [6]Parameter Description

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 11 of 37tCKLZ[9]Clock HIGH to Output Low-Z 1 1 nstSINTClock to INT Set Time 1 7.5 1 10 nstRINT

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 12 of 37 Test ClockTest Mode SelectTCKTMSTest Data-InTDITest Data-OutTDOtTCYCtTMSHtTLtTHtTMSStT

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 13 of 37Read Cycle[12, 13, 14, 15, 16]Notes: 12. OE is asynchronously controlled; all other inp

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 14 of 37Bank Select Read[17, 18] Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22]Notes: 17. In

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 15 of 37 Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] Read with Address Counter Advanc

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 16 of 37Write with Address Counter Advance [24, 25]Note: 25. CE0 = LB = UB = R/W = VIL; CE1 = C

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 17 of 37Counter Reset [21, 26, 27]Notes: 26. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CN

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 18 of 37 Load and Read Address Counter[28]Notes: 28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTR

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 19 of 37 Load and Read Mask Register [32]Notes: 32. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRS

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 2 of 37 Functional DescriptionThe Quadport Datapath Switching Element (DSE) family offersfour p

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 20 of 37 Port 1 Write to Port 2 Read[34, 35, 36]Notes: 34. CE0 = OE = LB = UB = CNTLD =VIL; CE1

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 21 of 37 Counter Interrupt [37, 38, 39] Mailbox Interrupt Timing[40, 41, 42, 43, 44]Notes: 37

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 22 of 37Table 1. Read/Write and Enable Operation (Any Port)[45, 46, 47]Inputs OutputsOperationO

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 23 of 37Master ResetThe QuadPort DSE device undergoes a complete reset bytaking its Master Rese

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 24 of 37Address Counter Control OperationsCounter enable inputs are provided to stall the opera

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 25 of 37Counter-Mask RegisterThe burst counter has a mask register that controls when andwhere

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 26 of 37address the entire memory array (depend on the value of the mask register) and loop bac

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 27 of 37The EXTEST, and SAMPLE/PRELOAD instructions can beused to capture the contents of the I

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 28 of 37number of TCK cycles depending on the TCK and CLKBISTfrequency. tCYC is total number of

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 29 of 37TAP Controller State Diagram (FSM)[53]Note: 53. The “0”/”1” next to each state represen

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 3 of 37counter is loaded with an external address when the port’sCounter Load pin (CNTLD) is as

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 30 of 37 JTAG/BIST TAP Controller Block Diagram Table 4. Identification Register DefinitionsIns

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 31 of 37 Table 5. Scan Registers SizesRegister Name Bit SizeInstruction (IR) 4Bypass (BYR) 1Ide

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 32 of 37 001001 chkr_r All ports read topological checkerboard data.001000 n_chkr_w Port 1 writ

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 33 of 37Table 9. Boundary Scan Order Cell # Signal Name Bump (Ball) ID2 A0_P4 K204 A1_P4 J196 A

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 34 of 37166 IO2_P1 Y5168 IO3_P1 W5170 IO4_P1 Y4172 IO5_P1 W4174 IO6_P1 Y3176 IO7_P1 W3178 IO8_P

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 35 of 37 330 IO13_P2 A4332 IO14_P2 B4334 IO15_P2 A3336 IO16_P2 B3338 IO17_P2 A2340 IO9_P1 C9342

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 36 of 37© Cypress Semiconductor Corporation, 2006. The information contained herein is subject

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 37 of 37Document History PageDocument Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE F

All Datasheets Cannot Be Modified Without Permission Copyright © Each Manufacturing Company This datasheet has been downloaded from: www.EEworld.c

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 4 of 37Addr.ReadPort 1 Operation-Control Logic Block DiagramR/WP1CE0P1CE1P1LBP1OEP1UBP1I/O9P1–I

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 5 of 37Pin Configuration272-ball Grid Array (BGA)Top ViewNote: 4. Central Leads are for thermal

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 6 of 37 Selection GuideCY7C0430CV–133CY7C0430CV–100 UnitfMAX2133[1]100 MHzMax Access Time (Cloc

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 7 of 37CNTRDP1CNTRDP2CNTRDP3CNTRDP4Counter Readback Input. When asserted LOW, the internal addr

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 8 of 37Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not t

CY7C0430BVCY7C0430CVDocument #: 38-06027 Rev. *B Page 9 of 37AC Test Load Note: 5. Test conditions: C = 10 pF.VTH=1.5VOUTPUTC(a) Normal LoadR = 50ΩZ0