Cypress Semiconductor Perform STK12C68 Bedienungsanleitung PDF herunterladen (Seite 13)

STK12C68

Document Number: 001-51027 Rev. *G Page 13 of 22

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows.

[18]

Parameter Alt Description

25 ns 35 ns 45 ns

Unit

Min Max Min Max Min Max

[14]

AVAV

STORE/RECALL initiation cycle time 25 – 35 – 45 – ns

[17]

AVEL

Address setup time 0 – 0 – 0 – ns

[17]

ELEH

Clock pulse width 20 – 25 – 30 – ns

HACE

[17]

ELAX

Address hold time 20 – 20 – 20 – ns

RECALL

RECALL duration – 20 – 20 – 20 s

Switching Waveform

Figure 12. CE Controlled Software STORE/RECALL Cycle

[18]

SCE

HACE

STORE

/ t

RECALL

DATA VALID

6 # SSERDDA1 # SSERDDA

HIGH IMPEDANCE

ADDRESS

DQ (DATA)

Notes

17. The software sequence is clocked on the falling edge of CE

without involving OE (double clocking aborts the sequence).

18. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE

must be HIGH during all six consecutive cycles.

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Cypress Semiconductor Perform STK12C68 Bedienungsanleitung Seite 13