Cypress Semiconductor STK14C88-5 Bedienungsanleitung PDF herunterladen (Seite 11)

STK14C88

Document Number: 001-52038 Rev. *D Page 11 of 21

nvSRAM Operation

The STK14C88 has two separate modes of operation: SRAM

mode and nonvolatile mode. In SRAM mode, the memory

operates as a standard-fast SRAM. In nonvolatile mode, data is

transferred from SRAM to nonvolatile elements (the STORE

operation) or from nonvolatile elements to SRAM (the RECALL

operation). In this mode, SRAM functions are disabled.

Noise Considerations

The STK14C88 is a high-speed memory and so must have a

high frequency bypass capacitor of approximately 0.1 F

connected between V

CAP

and V

, using leads and traces that

are as short as possible. As with all high-speed CMOS ICs,

careful routing of power, ground, and signals helps to prevent

noise problems.

SRAM Read

The STK14C88 performs a read cycle whenever E and G are

low, and W

and HSB are high. The address specified on pins

0-14

determines which of the 32,768 data bytes are accessed.

When the read is initiated by an address transition, the outputs

are valid after a delay of t

AVQV

(Read cycle #1). If the read is

initiated by E

or G, the outputs are valid at t

ELQV

or at t

GLQV

whichever is later (Read cycle #2). The data outputs repeatedly

respond to address changes within the t

AVQV

access time

without the need for transitions on any control input pins, and

remain valid until another address change or until E

or G is

brought high, or W

or HSB is brought low.

SRAM Write

A write cycle is performed whenever E and W are low, and HSB

is high. The address inputs must be stable prior to entering the

write cycle and must remain stable until either E

or W goes high

at the end of the cycle. The data on the common I/O pins DQ

0-7

are written into the memory if it is valid t

DVWH

before the end of

a W

controlled write or t

DVEH

before the end of an E controlled

write.

Keep G

high during the entire write cycle to avoid data bus

contention on common I/O lines. If G

is left low, internal circuitry

turns off the output buffers t

WLQZ

after W goes low.

Power Up RECALL

During power up, or after any low-power condition (V

CAP

RESET

), an internal RECALL request is latched. When V

CAP

again exceeds the sense voltage of V

SWITCH

, a RECALL cycle

is automatically initiated and takes t

RESTORE

to complete.

If the STK14C88 is in a write state at the end of power-up

RECALL, the SRAM data will be corrupted. To avoid this, a 10 k

resistor should be connected either between W

and system V

or between E

and system V

Software Nonvolatile STORE

The STK14C88 software STORE cycle is initiated by executing

sequential E

controlled read cycles from six specific address

locations. During the STORE cycle an erase of the previous

nonvolatile data is first performed, followed by a program of the

nonvolatile elements. The program operation copies the SRAM

data into nonvolatile memory. When a STORE cycle is initiated,

further input and output are disabled until the cycle is completed.

Because a sequence of reads from specific addresses is used

for STORE initiation, it is important that no other read or write

accesses intervene in the sequence, or the sequence will be

aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following read

sequence must be performed:

1. Read address 0E38 (hex) Valid READ

2. Read address 31C7 (hex) Valid READ

3. Read address 03E0 (hex) Valid READ

4. Read address 3C1F (hex) Valid READ

5. Read address 303F (hex) Valid READ

6. Read address 0FC0 (hex) Initiate STORE cycle

The software sequence must be clocked with E controlled reads.

After the sixth address in the sequence is entered, the STORE

cycle commences and the chip is disabled. Use only read cycles

in the sequence, although it is not necessary that G

be low for

the sequence to be valid. After the tSTORE cycle time is fulfilled,

the SRAM is again activated for read and write operation.

Software Nonvolatile RECALL

A software RECALL cycle is initiated with a sequence of read

operations in a manner similar to the software STORE initiation.

To initiate the RECALL cycle, the following sequence of E

controlled read operations must be performed:

1. Read address 0E38 (hex) Valid READ

2. Read address 31C7 (hex) Valid READ

3. Read address 03E0 (hex) Valid READ

4. Read address 3C1F (hex) Valid READ

5. Read address 303F (hex) Valid READ

6. Read address 0C63 (hex) Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared, and second, the nonvolatile information is transferred

into the SRAM cells. After the t

RECALL

cycle time, the SRAM is

again ready for read and write operations. The RECALL

operation in no way alters the data in the nonvolatile elements.

The nonvolatile data can be recalled an unlimited number of

times.

AutoStore Mode

The STK14C88 can be powered in one of three modes.

During normal AutoStore operation, the STK14C88 draws

current from V

to charge a capacitor connected to the V

CAP

pin. This stored charge is used by the chip to perform a single

STORE operation. After power up, when the voltage on the V

CAP

pin drops below V

SWITCH

, the part automatically disconnects the

CAP

pin from V

and initiate a STORE operation.

Not Recommended for New Designs

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