Cypress Semiconductor CYS25G0101DX-ATC Bedienungsanleitung PDF herunterladen

CYS25G0101DX

SONET OC-48 Transceiver

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 38-02009 Rev. *K Revised July 27, 2007

Features

■

SONET OC-48 operation

■

Bellcore and ITU jitter compliance

■

2.488 GBaud serial signaling rate

■

Multiple selectable loopback or loop through modes

■

Single 155.52 MHz reference clock

■

Transmit FIFO for flexible data interface clocking

■

16-bit parallel-to-serial conversion in transmit path

■

Serial-to-16-bit parallel conversion in receive path

■

Synchronous parallel interface

❐

LVPECL compliant

❐

HSTL compliant

■

Internal transmit and receive phase-locked loops (PLLs)

■

Differential CML serial input

❐

50 mV input sensitivity

❐

100

Ω

Internal termination and DC restoration

■

Differential CML serial output

❐

Source matched for 50

Ω

transmission lines (100

Ω

differential

transmission lines)

■

Direct interface to standard fiber optic modules

■

Less than 1.0W typical power

■

120-pin 14 mm × 14 mm TQFP

■

Standby power saving mode for inactive loops

■

0.25µ BiCMOS technology

■

Pb-free packages available

Functional Description

The CYS25G0101DX SONET OC-48 Transceiver is a commu-

nications building block for high speed SONET data communica-

tions. It provides complete parallel-to-serial and serial-to-parallel

conversion, clock generation, and clock and data recovery

operations in a single chip optimized for full SONET compliance.

Transmit Path

New data is accepted at the 16-bit parallel transmit interface at

a rate of 155.52 MHz. This data is passed to a small integrated

FIFO to allow flexible transfer of data between the SONET

processor and the transmit serializer. As each 16-bit word is read

from the transmit FIFO, it is serialized and sent out to the high

speed differential line driver at a rate of 2.488 Gbits/second.

Receive Path

As serial data is received at the differential line receiver, it is

passed to a clock and data recovery (CDR) PLL that extracts a

precision low jitter clock from the transitions in the data stream.

This bit rate clock is used to sample the data stream and receive

the data. Every 16-bit times, a new word is presented at the

receive parallel interface along with a clock.

Parallel Interface

The parallel I/O interface supports high speed bus communica-

tions using HSTL signaling levels to minimize both power

consumption and board landscape. The HSTL outputs are

capable of driving unterminated transmission lines of less than

70 mm and terminated 50Ω transmission lines of more than twice

that length.

The CYS25G0101DX Transceiver’s parallel HSTL I/O can also

be configured to operate at LVPECL signaling levels. This is

done externally by changing V

DDQ

, V

REF

and creating a simple

circuit at the termination of the transceiver’s parallel output

interface.

1 2 3 4 5 6 ... 16 17

SONET OC-48 Transceiver 1
CYS25G0101DX 10

Inhaltsverzeichnis

Seite 1 - SONET OC-48 Transceiver

CYS25G0101DXSONET OC-48 TransceiverCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600Document Number: 38-0

Seite 2

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 10 of 17AC WaveformsAC Test LoadsTable 5. DC Specifications—HSTL Parameter Description Test Condit

Seite 3

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 11 of 17AC Specifications Table 6. AC Specifications—Parallel InterfaceParameter Description Mi

Seite 4

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 12 of 17Jitter WaveformsThe Jitter Transfer Waveform of CYS25G0101DX follows. [12].Table 9. Jitter

Seite 5

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 13 of 17 Figure 6. CYS25G0101DX Reference Clock Phase Noise LimitsSwitching Waveforms Transmit In

Seite 6

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 14 of 17Typical IO Terminations Figure 7. Serial Input TerminationFigure 8. Serial Output termina

Seite 7

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 15 of 17Figure 12. AC Coupled Clock Oscillator TerminationFigure 13. Clock Oscillator Termination

Seite 8

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 16 of 17Ordering Information Speed Ordering Code Package Name Package Type Operating RangeStandard

Seite 9

Document Number: 38-02009 Rev. *K Revised July 27, 2007 Page 17 of 17PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks an

Seite 10 - CYS25G0101DX

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 2 of 17 16TXD[15:0]InputRegisterShifterTXCLKILOCKREFTX PLLX16FIFOIN±OUT±÷16(155.52 MHz)LOOPTIMETX B

Seite 11

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 3 of 17ClockingThe source clock for the transmit data path is selectable from either the recovered

Seite 12

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 4 of 17Pin ConfigurationThe pin configuration for 120-pin Thin Quad Flatpack follows. [1, 2]1234567

Seite 13

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 5 of 17Pin Descriptions CYS25G0101DX OC-48 SONET Transceiver Pin Name I/O Characteristics Signal De

Seite 14

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 6 of 17CYS25G0101DX OperationThe CYS25G0101DX is a highly configurable device designedto support re

Seite 15

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 7 of 17SerializerThe parallel data from the phase align buffer is passed to theSerializer that con

Seite 16

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 8 of 17Power Down ModeCYS25G0101DX provides a global power down signal PWRDN.When LOW, this sign

Seite 17

CYS25G0101DXDocument Number: 38-02009 Rev. *K Page 9 of 17 Table 2. DC Specifications—PowerParameter Description Test Conditions Typ Max UnitPowerICC

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Inhaltsverzeichnis

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