Document Number: 38-02009 Rev. *K Page 4 of 17
Pin Configuration
The pin configuration for 120-pin Thin Quad Flatpack follows.
[1, 2]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
27
29
30
31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61
62
65
64
63
70
69
68
67
66
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
LFI
RESET
DIAG LOOP
LINELO O P
LOOPA
VSSN
VCCN
VSSN
SD
LOCKREF
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
VSSN
VDDQ
RXD[6]
RXD[7]
VSSN
VDDQ
RXCLK
VSSN
VDDQ
NC
NC
NC
NC
VSSQ
N C
N C
VSSN
VDDQ
RXD[8]
RXD[9]
RXD[10]
RXD[11]
RXD[12]
RXD[13]
RXD
[14]
RXD[15]
VSSN
VDDQ
VCCN
VSSN
FIFO_ERR
FIFO_RST
TXD[15]
TXD[14]
TXD[13]
TXD[12]
TXCLKI
VSSN
VCCN
VREF
TXD[11]
TXD[10]
TXD[9]
TXD[8]
TXD[7]
TXD[6]
TXD[5]
TXD[4]
VSSQ
VCCQ
VSSN
VCCN
TXD[3]
TXD[2]
TXD[1]
TXD[0]
VSSN
VDDQ
TXCLKO
VS SN
VCCN
PW RD N
LO OPTIME
NC
REFC LK–
REFC LK+
VS SQ
VCCQ
NC
NC
NC
VCCQ
VSSQ
NC
VSSQ
VSSQ
VCCQ
VCCQ
O U T+
O U T–
VCCQ
CM_SER
VSSQ
IN–
IN+
VSSQ
VCCQ
VCCQ \NC*
VSSQ \NC*
VSSQ \NC*
NC
RXCP2
RXCN2
RXCP1
RXCN1
CYS25G0101DX
Top View
VSSN VSSN
NC
NC
NC
VSSQ
VCCQ
VCCQ
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
27
29
30
31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61
62
65
64
63
70
69
68
67
66
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
120
119
118
117
116
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
27
29
30
31 32 33 34 35 3 6 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61
62
65
64
63
70
69
68
67
66
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
LFI
RESET
DIAG LOOP
LINELO O P
LOOPA
VSSN
VCCN
VSSN
SD
LOCKREF
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
VSSN
VDDQ
RXD[6]
RXD[7]
VSSN
VDDQ
RXCLK
VSSN
VDDQ
NC
NC
NC
NC
VSSQ
N C
N C
VSSN
VDDQ
RXD[8]
RXD[9]
RXD[10]
RXD[11]
RXD[12]
RXD[13]
RXD
[14]
RXD[15]
VSSN
VDDQ
VCCN
VSSN
FIFO_ERR
FIFO_RST
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
LFI
RESET
DIAG LOOP
LINELO O P
LOOPA
VSSN
VCCN
VSSN
SD
LOCKREF
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
VSSN
VDDQ
RXD[6]
RXD[7]
VSSN
VDDQ
RXCLK
VSSN
VDDQ
NC
NC
NC
NC
VSSQ
N C
N C
VSSN
VDDQ
RXD[8]
RXD[9]
RXD[10]
RXD[11]
RXD[12]
RXD[13]
RXD
[14]
RXD[15]
VSSN
VDDQ
VCCN
VSSN
FIFO_ERR
FIFO_RST
TXD[15]
TXD[14]
TXD[13]
TXD[12]
TXCLKI
VSSN
VCCN
VREF
TXD[11]
TXD[10]
TXD[9]
TXD[8]
TXD[7]
TXD[6]
TXD[5]
TXD[4]
VSSQ
VCCQ
VSSN
VCCN
TXD[3]
TXD[2]
TXD[1]
TXD[0]
VSSN
VDDQ
TXCLKO
VS SN
VCCN
PW RD N
LO OPTIME
NC
REFC LK–
REFC LK+
VS SQ
VCCQ
NC
NC
NC
VCCQ
VSSQ
NC
VSSQ
VSSQ
VCCQ
VCCQ
O U T+
O U T–
VCCQ
CM_SER
VSSQ
IN–
IN+
VSSQ
VCCQ
VCCQ \NC*
VSSQ \NC*
VSSQ \NC*
NC
RXCP2
RXCN2
RXCP1
RXCN1
CYS25G0101DX
Top View
VSSN VSSN
NC
NC
NC
VSSQ
VCCQ
VCCQ
VCCQ
Figure 2. 120-Pin Thin Quad Flatpack Pin Configuration
Notes
1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of
the device.
2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ.
Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
(53 Seiten)
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