Cypress Semiconductor SL811HS Spezifikationen PDF herunterladen (Seite 14)

SL811HS

Document #: 38-08008 Rev. *A Page 14 of 29

5.3.6 USB Address Register, Reserved, Address [07H]

This register is reserved for the device USB Address in Slave operation. It should not be written by the user.

5.3.7 Interrupt Status Register, Address [0DH]

The ISR is a Read/Write register providing interrupt status. Interrupts can be cleared by writing to this register. To clear a specific

interrupt, the register is written with corresponding bit set to “1.”

• Bit 5 is provided to support USB cable Insertion/Removal for the SL811HS in Host Mode. This bit is set when a transition from

SE0 to IDLE (device inserted) or IDLE to SE0 (device removed) occurs on the bus.

• Bit 6 is shared between Device Detection status and Resume detection interrupt. When bit-6 of register 05H is set to one, this

bit will be the Resume detection Interrupt bit. Otherwise, this bit is used to indicate the presence of a Device, “1” = device “Not

present” and “0” = device “Present.” In this mode this bit should be checked along with bit 5 to determine whether a device

has been inserted or removed.

• Bit 7 provides continuous USB Data+ line status. Once it has been determined that a device has been inserted as described

above with bits 5 and 6, bit 7 can be used to detect if the inserted device is low- or full-speed.

5.3.8 Current Data Set Register/Hardware Revision/SOF Counter LOW, Address [0EH]

• This register has two modes: a Read from this register indicates the current SL811HS silicon revision.

• Writing to this register will set up auto generation of SOF to all connected peripherals. This counter is based on the 12-MHz

clock. To set up a 1-ms timer interval, the software must set up both SOF counter registers to the proper values.

• Example. To set up SOF for 1-ms interval, SOF counter register 0EH should be set to E0H.

Bit Position Bit Name Function

0 USB-A USB-A Done Interrupt

1 USB-B USB-B Done Interrupt

2 Reserved

3 Reserved

4 SOF timer 1 = Interrupt on 1-ms SOF Timer

5 Insert/Remove Slave Insert/Remove Detection

6 Device Detect/Resume Device Detect/Resume Interrupt

7 D+ Value of the Data+ Pin

Bit Position Bit Name Function

0 Reserved Reserved for slave

1 Reserved Reserved for slave

2 Reserved Read will be zero

3 Reserved Read will be zero

4–7 HW Revision SL11H Read = 0H, SL811HS rev1.2 Read = 1H, SL811HS

rev1.5 Read = 2

Bit Position Bit Name Function

0–7 SOF LOW Counter Register Write-only to set SOF LOW Counter Register, OEH

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 28 29

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Cypress Semiconductor SL811HS Spezifikationen Seite 14