Cypress Semiconductor SL811HS Spezifikationen PDF herunterladen (Seite 21)

SL811HS

Document #: 38-08008 Rev. *A Page 21 of 29

Notes:

12. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.

6.2.4 Package Markings (SL811HST-AC)

YYWW = Date code

XXXX = Product code

X.X = Silicon revision number

33 BIDIR D6 Data 6. Microprocessor Data/(Address) Bus.

34 NC NC NC

35 NC NC NC

36 NC NC NC

37 NC NC NC

38 NC NC NC

39 BIDIR D7 Data 7. Microprocessor Data/(Address) Bus.

40 IN M/S Master/Slave Mode Select. “1” selects Slave. “0” = Master.

41 VDD +3.3 VDC SL811HST-AC Device V

Power.

42 IN A0 A0 = “0.” Selects address pointer. Reg.A0 = “1.” Selects data buffer or

[12]

43 IN nDACK DMA Acknowledge. An active LOW input used to interface to an

external DMA controller. DMA is enabled only in slave mode. In host

mode, pin should be tied HIGH (logic “1”) .

44 OUT nDRQ DMA Request. An active LOW output used with an external DMA

controller. nDRQ and nDACK form the handshake for DMA data

transfers. In host mode, pin must be left unconnected .

45 IN NRD Read Strobe Input. An active LOW input used with nCS to Read

registers/data memory.

46 NC NC NC

47 NC NC NC

48 NC NC NC

Table 6-2. SL811HST-AC Pin Assignments and Definitions (continued)

Pin No. Pin Type Pin Name Pin Description

SL811HST

YYWW-X.X

XXXX

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29

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