Document Number: 38-08036 Rev. *E Page 8 of 33
Pin Information
56-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled “P”) is capable of Digital I/O. However, Vss and Vdd are not capable of Digital I/O.
Table 2. 56-Pin Part Pinout (QFN-MLF SAWN)
[1]
Pin
No.
Type
Name Description
Figure 3. CY7C64215 56-Pin enCoRe III Device
Digital Analog
1 I/O I, M P2[3] Direct Switched Capacitor Block Input.
2 I/O I, M P2[1] Direct Switched Capacitor Block Input.
3 I/O M P4[7]
4 I/O M P4[5]
5 I/O M P4[3]
6 I/O M P4[1]
7 I/O M P3[7]
8 I/O M P3[5]
9 I/O M P3[3]
10 I/O M P3[1]
11 I/O M P5[7]
12 I/O M P5[5]
13 I/O M P5[3]
14 I/O M P5[1]
15 I/O M P1[7] I2C Serial Clock (SCL).
16 I/O M P1[5] I2C Serial Data (SDA).
17 I/O M P1[3]
18 I/O M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
19 Power Vss Ground Connection.
20 USB D+
21 USB D-
22 Power Vdd Supply Voltage.
23 I/O P7[7]
24 I/O P7[0]
25 I/O M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
26 I/O M P1[2]
27 I/O M P1[4] Optional External Clock Input EXTCLK.
28 I/O M P1[6]
29 I/O M P5[0]
Pin
No.
Type
Name Description
30 I/O M P5[2] Digital Analog
31 I/O M P5[4] 44 I/O M P2[6] External Voltage Reference (VREF) Input.
32 I/O M P5[6] 45 I/O I, M P0[0] Analog Column Mux Input.
33 I/O M P3[0] 46 I/O I, M P0[2] Analog Column Mux Input and Column Output.
34 I/O M P3[2] 47 I/O I, M P0[4] Analog Column Mux Input and Column Output.
35 I/O M P3[4] 48 I/O I, M P0[6] Analog Column Mux Input.
36 I/O M P3[6] 49 Power Vdd Supply Voltage.
37 I/O M P4[0] 50 Power Vss Ground Connection.
38 I/O M P4[2] 51 I/O I, M P0[7] Analog Column Mux Input.
39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog Column Mux Input and Column Output
40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog Column Mux Input and Column Output.
41 I/O I, M P2[0] Direct Switched Capacitor Block Input. 54 I/O I, M P0[1] Analog Column Mux Input.
42 I/O I, M P2[2] Direct Switched Capacitor Block Input. 55 I/O M P2[7]
43 I/O M P2[4] External Analog Ground (AGND) Input. 56 I/O MP2[5]
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
1. The center pad on the QFN-MLF package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
QFN-MLF
(Top View)
A, I, M, P2[3]
A, I, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
D+
D-
Vdd
P7[7]
P7[0]
M, I2C SDA, P1[0]
M, P1[2]
M, P1[4]
M, P1[6]
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2[4], M
P2[6], M
P0[0], A, I, M
P0[2], A, I, M
P0[4], A, I, M
P0[6], A, I, M
Vdd
Vss
P0[7], A, I, M
P0[5], A, IO, M
P0[3], A, IO, M
P0[1], A, I, M
P2[7], M
P2[5], M
43
44
45
46
47
48
49
50
51
52
53
54
55
56
P2[2], A, I, M
P2[0], A, I, M
P4[6] , M
P4[4] , M
P4[2] , M
P4[0] , M
P3[6] , M
P3[4] , M
P3[2] , M
P3[0] , M
P5[6] , M
P5[4] , M
P5[2] , M
P5[0] , M
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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