Cypress Semiconductor enCoRe CY7C64215 Bedienungsanleitung PDF herunterladen (Seite 5)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

Clocking

The CY7C64x13 microcontroller requires an external crystal

or an external clock for operation. When an external crystal is

used, it provides the reference frequency for the internal PLL.

The load caps and bias resistors are internal to the chip. They

also impose a requirement on the load capacitance of the

crystal (15–18 pF). When an external oscillator/clock is used,

the clock is to be connected to the XTALIN pin with the

XTALOUT pin left open. The CPU operates at 12 MHz.

The CY7C64215 microcontroller has an internal oscillator

that provides a 24 MHz clock, accurate to 8% over tempera-

ture and voltage. The enCoRe III system clock can be

sourced by the internal 24 MHz clock or by an accurate exter-

nal clock. The system clock in turn can be divided by pro-

grammable dividers and can source different modules in the

device. This can be done using the PSoC Designer tool,

Device Editor view – global resources section. The external

clock input at P1[4] can be enabled by setting bit 2 in the

OSC_CR2 register at location 1,E2h.

When communicating using USB, the 24 MHz IMO can self

tune to an accuracy of ±0.25%. To enable this (required

unless an accurate external clock is used), the ‘EnableLock’

bit (bit 1) in register USB_CR1 (1,C1h) should be set by firm-

ware. This is provided in the USB_Start API function.

The enCoRe III CPU can run at eight different speeds (24

MHz to 93.7 KHz); this allows for performance and power

requirements to be tailored to the desired application. This is

made possible by using bits [2:0] in the OSC_CR0 register

(location 1,E0h). This can also be achieved in the develop-

ment tool – Device Editor view, global resources section.

The CY7C64215 also has an internal 32 KHz low power

oscillator for sleep timer and watchdog timer. These clocks,

along with the programmable clock dividers, make it possible

to have a wide range of frequencies in the microcontroller.

Memory Organization

The CY7C64x13 has 8 KB of PROM and 256 bytes of data

RAM. The SRAM is partitioned into Data Stack, Program

Stack, user variables, and USB endpoint FIFOs. The end-

point FIFOs can be configured (size and number of end-

points) by writing to bits 7 and 6 in the USB Status and

Control register (0x1F). The unused SRAM locations can be

used for user variables. The program stack starts at 00h and

grows forward. The data stack grows backwards and so firm-

ware must write an appropriate value into the DSP register to

prevent conflict with the endpoint FIFO address.

Figure 3. CY7C64x13 Stack/SRAM/Endpoint FIFO Setup

Timer The CY7C64x13 has a 12-bit free-running timer that

is clocked with a 1 MHz source clock. Two interrupts

are provided at 128 μs and 1.024 ms.

The user has available digital peripherals to build 8, 16,

24 bits wide timer (depending on resource availability),

with interrupts at desired intervals. Additionally, the

enCoRe III also has a sleep timer (sleep timer interrupt, to

wake up periodically and poll for interrupts) and watchdog

timer as part of the system resources.

Development Tools Uses the CY3654 platform board and the CY3654-

P03 personality board for to assist in emula-

tion/debugging during firmware development. Emula-

tion is achieved through an on-board FPGA

programmed with the user firmware. The CY3654-

P03 personality board can also accommodate flex-

pod to aid in on-board emulation.

Based on Cypress PSoC development suite. GUI based

suite (USB Setup Wizard) to develop/build USB function-

ality. Uses ICE cube and the CY3664 application board

for emulation/debugging. Actual target silicon pro-

grammed with user firmware is used in emulation. On-

board emulation is made possible using ICE and the

CY7C64215 flex-pods.

Programming Out of system programming only. Use of a separate

pin for programming and high programming voltages

(12V).

In-system programming possible using programming

headers on the board. Programming voltage as low as

2.7V.

Supply Voltage 4.0 to 5.25V. For reliable USB operation, the supply

voltage should be between 4.35 and 5.25V.

3.0 to 5.25V. Can operate USB at 3.3V powered exter-

nally. Mechanism must be provided to detect Vbus con-

nection to engage the D+ pull up and start

communications.

Features/Characteristics CY7C64x13 CY7C64215

Address

0x00

Address

0xFF

Program Stack Growth

Data Stack Growth

User Variables

USB FIFO space for five endpoints

1 2 3 4 5 6 7 8 9 10 ... 15 16

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