Cypress Semiconductor Perform CY7C1380D Spezifikationen PDF herunterladen (Seite 18)

3–6 Chapter 3: Building the SOPC System

Specify the SOPC Builder System Components

Nios II System Architect Design Tutorial © June 2009 Altera Corporation

Preliminary

3. Click Finish.

4. In the Module Name column, right-click the Avalon-MM Clock Crossing Bridge

component’s name, click Rename, and rename the new component

cpu_ddr_clock_bridge.

5. In the Connections column, ensure that the cpu_ddr_clock-bridge/m1 master

port is connected to the ddr_sdram/s1 slave port.

By default, the cpu/instruction_master and cpu/data_master ports are

connected to the cpu_ddr_clock_bridge/s1 slave port.

If one of these connections is absent, click on the open dot at the intersection of the

relevant signal lines to make the connection. A filled dot at the intersection

indicates a connection is present. Move your mouse to the Connections column to

make the connection dots visible.

Figure 3–5 shows the desired cpu_ddr_clock_bridge port connections.

Figure 3–4. Avalon-MM Clock Crossing Bridge Component Settings

Figure 3–5. cpu_ddr_clock_bridge Component Connections

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Cypress Semiconductor Perform CY7C1380D Spezifikationen Seite 18