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3–8 Chapter 3: Building the SOPC System

Specify the SOPC Builder System Components

Nios II System Architect Design Tutorial © June 2009 Altera Corporation

Preliminary

7. In the Connections column, ensure that your system does not have the following

connection:

■ lcd_sgdma/csr to cpu/data_master — Because the Nios II processor and

the SGDMA component are in different clock domains, the lcd_sgdma/csr

port must connect to the clock-crossing bridge and not directly to the Nios II

processor.

Click on the dot at the intersection of the relevant signal lines to toggle the connection.

A filled dot at the intersection indicates a connection is present, and an open dot

indicates a connection is severed. Move your mouse to the Connections column to

make the connection dots visible.

Figure 3–5 shows the desired lcd_sgdma port connections. The lcd_sgdma/out

port to lcd_ta_sgdma_to_fifo/in port connection does not appear in the figure.

After you perform these instructions, your SOPC Builder system contains all of the

components it requires to implement your design requirements. Now you must

resolve the system validation errors.

Table 3–2. SGDMA Component Connections

From To Description

lcd_sgdma/csr cpu_ddr_clock_bridge/m1 Because the Nios II processor and

the SGDMA component are in

different clock domains, the

lcd_sgdma/csr port must connect

to the clock-crossing bridge. In

“Coordinate Components in the

System”, you set the SGDMA

component to use the same clock as

the DDR SDRAM.

lcd_sgdma/descriptor_read ddr_sdram/s1 The SGDMA fetches the read descriptors

from the DDR SDRAM.

lcd_sgdma/descriptor_write ddr_sdram/s1 The SGDMA fetches the write descriptors

from the DDR SDRAM.

lcd_sgdma/m_read ddr_sdram/s1 The SGDMA fetches the video frame

buffer data from the DDR SDRAM.

lcd_sgdma/out lcd_ta_sgdma_to_fifo/in The SGDMA sends the data to the video

pipeline.

Figure 3–7. lcd_sgdma Component Connections

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