Cypress Semiconductor CY7C1364C Bedienungsanleitung PDF herunterladen (Seite 7)

CY7C1364C

Document Number: 001-74592 Rev. *B Page 7 of 29

safety precaution, DQs are automatically tri-stated whenever a

Write cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1364C provides a two-bit wraparound counter, fed by

[1:0]

, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed

specifically to support Intel Pentium applications. The linear

burst sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment the

burst counter to the next address in the burst sequence. Both

Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE

, CE

, ADSP, and ADSC must remain inactive for the duration of

ZZREC

after the ZZ input returns LOW

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

DDZZ

Sleep mode standby current ZZ > V

– 0.2 V – 50 mA

ZZS

Device operation to ZZ ZZ > V

– 0.2 V – 2t

CYC

ZZREC

ZZ recovery time ZZ < 0.2 V 2t

CYC

–ns

ZZI

ZZ Active to Sleep current This parameter is sampled – 2t

CYC

RZZI

ZZ Inactive to exit Sleep current This parameter is sampled 0 – ns

1 2 3 4 5 6 7 8 9 10 11 12 ... 29 30

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