Cypress Semiconductor Perform CY7C1380D Bedienungsanleitung

18-Mbit (512K x 36/1M x 18) Pipelined SRAMCY7C1380D, CY7C1380FCY7C1382D, CY7C1382FCypress Semiconductor Corporation • 198 Champion Court • San Jose,

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 10 of 30Truth Table for Read/Write [4, 9]Function (CY7C1380D/CY7C1380F) GW B

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 11 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1380D/CY7C1382D incor

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 12 of 30When the TAP controller is in the Capture-IR state, the twoleast sig

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 13 of 30When this scan cell, called the “extest output bus tri-state,” islat

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 14 of 303.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 15 of 30Identification Register DefinitionsInstruction FieldCY7C1380D/CY7C13

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 16 of 30119-Ball BGA Boundary Scan Order[14, 15] Bit # Ball ID Bit # Ball ID

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 17 of 30165-Ball BGA Boundary Scan Order[14, 16]Bit # Ball ID Bit # Ball ID

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 18 of 30Maximum RatingsExceeding the maximum ratings may impair the useful l

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 19 of 30Capacitance [19]Parameter Description Test Conditions100 TQFPPackage

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 2 of 30Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36)Logic Block

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 20 of 30Switching Characteristics Over the Operating Range [20, 21]Parameter

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 21 of 30Switching Waveforms Read Cycle Timing [26]tCYCtCLCLKADSPtADHtADSADDR

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 22 of 30Write Cycle Timing [26, 27]Switching Waveforms (continued)tCYCtCLCL

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 23 of 30Read/Write Cycle Timing [26, 28, 29]Switching Waveforms (continued)

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 24 of 30ZZ Mode Timing [30, 31]Switching Waveforms (continued)tZZISUPPLYCLK

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 25 of 30Ordering InformationNot all of the speed, package and temperature ra

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 26 of 30250 CY7C1380D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 27 of 30Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 28 of 30Figure 2. 119-ball BGA (14 x 22 x 2.4 mm) (51-85115)Package Diagrams

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 29 of 30© Cypress Semiconductor Corporation, 2006-2007. The information cont

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 3 of 30Pin Configurations AAAAA1A0NC/72MNC/36MVSSVDDAAAAAAAADQPBDQBDQBVDDQVS

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 30 of 30Document History PageDocument Title: CY7C1380D/CY7C1382D/CY7C1380F/C

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 4 of 30Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 5 of 30Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable)CY

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 6 of 30Pin DefinitionsName IO DescriptionA0, A1, A Input-SynchronousAddress

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 7 of 30Functional OverviewAll synchronous inputs pass through input register

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 8 of 30presented to A is loaded into the address register and theaddress adv

CY7C1380D, CY7C1380FCY7C1382D, CY7C1382FDocument #: 38-05543 Rev. *E Page 9 of 30Truth Table [4, 5, 6, 7, 8]Operation Add. Used CE1CE2CE3ZZ ADSP ADSC