Cypress Semiconductor CY8C24094 Bedienungsanleitung PDF herunterladen (Seite 12)

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Document Number: 38-12018 Rev. AD Page 12 of 61

8.5 100-Ball VFBGA Part Pinout

The 100-ball VFBGA part is for the CY8C24994 PSoC device.

Table 6. 100-Ball Part Pinout (VFBGA)

No.

Digital

Analog

Name Description

No.

Digital

Analog

Name Description

A1 Power V

Ground connection F1 NC No connection. Pin must be left floating

A2 Power V

Ground connection F2 I/O M P5[7]

A3 NC No connection. Pin must be left floating F3 I/O M P3[5]

A4 NC No connection. Pin must be left floating F4 I/O M P5[1]

A5 NC No connection. Pin must be left floating F5 Power V

Ground connection

A6 Power V

Supply voltage F6 Power V

Ground connection

A7 NC No connection. Pin must be left floating F7 I/O M P5[0]

A8 NC No connection. Pin must be left floating F8 I/O M P3[0]

A9 Power V

Ground connection F9 XRES Active high pin reset with internal pull-down

A10 Power V

Ground connection F10 I/O P7[1]

B1 Power V

Ground connection G1 NC No connection. Pin must be left floating

B2 Power V

Ground connection G2 I/O M P5[5]

B3 I/O I, M P2[1] Direct switched capacitor block input G3 I/O M P3[3]

B4 I/O I, M P0[1] Analog column mux input G4 I/O M P1[7] I

C SCL

B5 I/O I, M P0[7] Analog column mux input G5 I/O M P1[1] I

C SCL, ISSP SCLK

[11]

B6 Power V

Supply voltage G6 I/O M P1[0] I

C SDA, ISSP SDATA

[11]

B7 I/O I, M P0[2] Analog column mux input G7 I/O M P1[6]

B8 I/O I, M P2[2] Direct switched capacitor block input G8 I/O M P3[4]

B9 Power V

Ground connection G9 I/O M P5[6]

B10 Power V

Ground connection G10 I/O P7[2]

C1 NC No connection. Pin must be left floating H1 NC No connection. Pin must be left floating

C2 I/O M P4[1] H2 I/O M P5[3]

C3 I/O M P4[7] H3 I/O M P3[1]

C4 I/O M P2[7] H4 I/O M P1[5] I

C SDA

C5 I/O I/O, M P0[5] Analog column mux input and column output H5 I/O M P1[3]

C6 I/O I, M P0[6] Analog column mux input H6 I/O M P1[2]

C7 I/O I, M P0[0] Analog column mux input H7 I/O M P1[4] Optional EXTCLK

C8 I/O I, M P2[0] Direct switched capacitor block input H8 I/O M P3[2]

C9 I/O M P4[2] H9 I/O M P5[4]

C10 NC No connection. Pin must be left floating H10 I/O P7[3]

D1 NC No connection. Pin must be left floating J1 Power V

Ground connection

D2 I/O M P3[7] J2 Power V

Ground connection

D3 I/O M P4[5] J3 USB D+

D4 I/O M P2[5] J4 USB D–

D5 I/O I/O, M P0[3] Analog column mux input and column output J5 Power V

Supply voltage

D6 I/O I,M P0[4] Analog column mux input J6 I/O P7[7]

D7 I/O M P2[6] External VREF input J7 I/O P7[0]

D8 I/O M P4[6] J8 I/O M P5[2]

D9 I/O M P4[0] J9 Power V

Ground connection

D10 NC No connection. Pin must be left floating J10 Power V

Ground connection

E1 NC No connection. Pin must be left floating K1 Power V

Ground connection

E2 NC No connection. Pin must be left floating K2 Power V

Ground connection

E3 I/O M P4[3] K3 NC No connection. Pin must be left floating

E4 I/O I, M P2[3] Direct switched capacitor block input K4 NC No connection. Pin must be left floating

E5 Power V

Ground connection K5 Power V

Supply voltage

E6 Power V

Ground connection K6 I/O P7[6]

E7 I/O M P2[4] External AGND input K7 I/O P7[5]

E8 I/O M P4[4] K8 I/O P7[4]

E9 I/O M P3[6] K9 Power V

Ground connection

E10 NC No connection. Pin must be left floating K10 Power V

Ground connection

LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No connection. Pin must be left floating.

Note

11. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 60 61

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