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CY8C24223A, CY8C24423A

Document Number: 001-52469 Rev. *H Page 3 of 50

PSoC Functional Overview

The PSoC family consists of many programmable

system-on-chips with on-chip Controller devices. These devices

are designed to replace multiple traditional microcontroller unit

(MCU)-based system components with one, low cost single-chip

programmable device. PSoC devices include configurable

blocks of analog and digital logic, and programmable

interconnects. This architecture makes it possible for the user to

create customized peripheral configurations that match the

requirements of each individual application. Additionally, a fast

central processing unit (CPU), flash program memory, SRAM

data memory, and configurable I/O are included in a range of

convenient pinouts and packages.

The PSoC architecture, as shown in the Logic Block Diagram on

page 1, is comprised of four main areas: PSoC core, digital

system, analog system, and system resources. Configurable

global buses allow all the device resources to be combined into

a complete custom system. Each CY8C24x23A PSoC device

includes four digital blocks and six analog blocks. Depending on

the PSoC package, up to 24 GPIOs are also included. The

GPIOs provide access to the global digital and analog

interconnects.

PSoC Core

The PSoC core is a powerful engine that supports a rich feature

set. The core includes a CPU, memory, clocks, and configurable

GPIO.

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four-million instructions per second (MIPS)

8-bit Harvard-architecture microprocessor. The CPU uses an

interrupt controller with multiple vectors, to simplify programming

of real time embedded events. Program execution is timed and

protected using the included sleep timer and watchdog timer

(WDT).

Memory includes 4 KB of flash for program storage and 256

bytes of SRAM for data storage. Program flash uses four

protection levels on blocks of 64 bytes, allowing customized

software IP protection.

The PSoC device incorporates flexible internal clock generators,

including a 24-MHz internal main oscillator (IMO) accurate to

±5% over temperature and voltage. A low-power 32-kHz internal

low-speed oscillator (ILO) is provided for the sleep timer and

WDT. If crystal accuracy is desired, the 32.768-kHz external

crystal oscillator (ECO) is available for use as a real time clock

(RTC) and can optionally generate a crystal-accurate 24-MHz

system clock using a PLL. The clocks, together with

programmable clock dividers (as a system resource), provide the

flexibility to integrate almost any timing requirement into the

PSoC device.

PSoC GPIOs provide connection to the CPU, digital, and analog

resources of the device. Each pin’s drive mode may be selected

from eight options, allowing great flexibility in external inter-

facing. Every pin also has the capability to generate a system

interrupt.

Digital System

The digital system is composed of four digital PSoC blocks. Each

block is an 8-bit resource that can be used alone or combined

with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,

which are called user modules.

Figure 1. Digital System Block Diagram

Digital peripheral configurations include:

■ PWMs (8- to 32-bit)

■ PWMs with dead band (8- to 24-bit)

■ Counters (8- to 32-bit)

■ Timers (8- to 32-bit)

■ Full- or half-duplex 8-bit UART with selectable parity

■ SPI master and slave

■ I

C master, slave, or multimaster (implemented in a dedicated

C block)

■ Cyclical redundancy checker/generator (16-bit)

■ Infrared Data Association (IrDA)

■ PRS generators (8- to 32-bit)

The digital blocks can be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow for signal multiplexing and for performing logic

operations. This configurability frees your designs from the

constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows the optimum

choice of system resources for your application. Family

resources are shown in Table 1 on page 5.

DIGITAL SYSTEM

To System Bus

Digital PSoC Block Array

To Analog

System

Row Input

Configuration

Row Output

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 2

Port 1

Port 0

1 2 3 4 5 6 7 8 ... 50 51

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