Cypress Semiconductor NoBL CY7C1462AV25 Bedienungsanleitung PDF herunterladen (Seite 10)

CY7C1460AV25

CY7C1462AV25

Document Number: 38-05354 Rev. *J Page 10 of 31

Partial Write Cycle Description

The partial write cycle description table for CY7C1460AV25 follows.

[8, 9, 10, 11]

Function (CY7C1460AV25) WE BW

Read H X X X X

Write – no bytes written L H H H H

Write byte a – (DQ

and

DQP

)LHHHL

Write byte b – (DQ

and

DQP

)LHHLH

Write bytes b, a L H H L L

Write byte c – (DQ

and

DQP

)LHLHH

Write bytes c, a L H L H L

Write bytes c, b L H LL L H

Write bytes c, b, a L H L L L

Write byte d – (DQ

and

DQP

)LLHHH

Write bytes d, a L L H H L

Write bytes d, b L L H L H

Write bytes d, b, a L L H L L

Write bytes d, c L L L H H

Write bytes d, c, a L L L H L

Write bytes d, c, b L L L L H

Write all bytes LLLLL

Notes

8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE

stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies

that the desired byte write selects are asserted, see Write Cycle Description table for details.

9. Write is defined by WE

and BW

. See Write Cycle Description table for details.

10. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

11. Table only lists a partial listing of the byte write combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 30 31

CY7C1460AV25 1
CY7C1462AV25 1

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