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CY7C1365C
9-Mbit (256 K × 32)
Flow-Through Sync SRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-74584 Rev. *C Revised October 25, 2012
9-Mbit (256 K × 32) Flow-Through Sync SRAM
Features
256 K × 32 common I/O
3.3 V core power supply (V
DD
)
2.5 V/3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Supports 3.3 V I/O level
Available in 165-Ball FBGA package
“ZZ” Sleep Mode option
IEEE 1149.1 JTAG-compatible boundary scan
Functional Description
The CY7C1365C is a 256 K × 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE
1
), depth-expansion
Chip Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC,
ADSP
, and ADV), Write Enables (BW[A:D], and BWE), and
Global Write (GW
). Asynchronous inputs include the Output
Enable (OE
) and the ZZ pin
.
The CY7C1365C allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP
) or the cache Controller Address Strobe
(ADSC
) inputs. Address advancement is controlled by the
Address Advancement (ADV
) input.
Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
) or Address
Strobe Controller (ADSC
) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1365C operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Description 133 MHz Unit
Maximum Access Time 6.5 ns
Maximum Operating Current 250 mA
Maximum Standby Current 40 mA
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Inhaltsverzeichnis

Seite 1 - Flow-Through Sync SRAM

CY7C1365C9-Mbit (256 K × 32)Flow-Through Sync SRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docum

Seite 2

CY7C1365CDocument Number: 001-74584 Rev. *C Page 10 of 30Truth Table for Read/WriteThe Truth Table for Read/Write for CY7C1365C follows. [6, 7]Functi

Seite 3

CY7C1365CDocument Number: 001-74584 Rev. *C Page 11 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1365C incorporates a serial boundary scan tes

Seite 4

CY7C1365CDocument Number: 001-74584 Rev. *C Page 12 of 30TAP Instruction SetOverviewEight different instructions are possible with the three-bitinstr

Seite 5

CY7C1365CDocument Number: 001-74584 Rev. *C Page 13 of 30TAP Controller State DiagramThe 0/1 next to each state represents the value of TMS at the ri

Seite 6

CY7C1365CDocument Number: 001-74584 Rev. *C Page 14 of 30TAP Controller Block DiagramTAP TimingBypass Register0Instruction Register012Identication R

Seite 7

CY7C1365CDocument Number: 001-74584 Rev. *C Page 15 of 303.3 V TAP AC Test ConditionsInput pulse levels ...

Seite 8

CY7C1365CDocument Number: 001-74584 Rev. *C Page 16 of 30TAP DC Electrical Characteristics and Operating Conditions(0 °C < TA < +70 °C; VDD = 3

Seite 9

CY7C1365CDocument Number: 001-74584 Rev. *C Page 17 of 30Instruction CodesInstruction Code DescriptionEXTEST 000 Captures I/O ring contents. Places t

Seite 10 - CY7C1365C

CY7C1365CDocument Number: 001-74584 Rev. *C Page 18 of 30Boundary Scan Order165-ball FBGACY7C1365C (256 K × 32) Bit # Ball ID Signal Name Bit # Ball

Seite 11 - TAP Registers

CY7C1365CDocument Number: 001-74584 Rev. *C Page 19 of 30Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. User guide

Seite 12 - TAP Instruction Set

CY7C1365CDocument Number: 001-74584 Rev. *C Page 2 of 30ADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFFERSINPUTREGISTERS

Seite 13

CY7C1365CDocument Number: 001-74584 Rev. *C Page 20 of 30ISB3Automatic CE Power-Down Current – CMOS InputsMax VDD, Device Deselected, VIN  VDDQ – 0.

Seite 14

CY7C1365CDocument Number: 001-74584 Rev. *C Page 21 of 30Switching CharacteristicsOver the Operating RangeParameter [15, 16]Description-133UnitMin Ma

Seite 15

CY7C1365CDocument Number: 001-74584 Rev. *C Page 22 of 30Timing DiagramsFigure 3. Read Cycle Timing [21]tCYCtCLCLKtADHtADSADDRESStCHtAHtASA1tCEHtCES

Seite 16

CY7C1365CDocument Number: 001-74584 Rev. *C Page 23 of 30Figure 4. Write Cycle Timing [22, 23]Timing Diagrams (continued)tCYCtCLCLKtADHtADSADDRESStC

Seite 17

CY7C1365CDocument Number: 001-74584 Rev. *C Page 24 of 30Figure 5. Read/Write Timing [24, 25, 26]Timing Diagrams (continued)tCYCtCLCLKtADHtADSADDRES

Seite 18

CY7C1365CDocument Number: 001-74584 Rev. *C Page 25 of 30Figure 6. ZZ Mode Timing [27, 28]Timing Diagrams (continued)tZZISUPPLYCLKZZtZZRECALL INPUTS

Seite 19

CY7C1365CDocument Number: 001-74584 Rev. *C Page 26 of 30Ordering InformationNot all of the speed, package and temperature ranges are available. Plea

Seite 20

CY7C1365CDocument Number: 001-74584 Rev. *C Page 27 of 30Package DiagramFigure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter)

Seite 21

CY7C1365CDocument Number: 001-74584 Rev. *C Page 28 of 30Acronyms Document ConventionsUnits of MeasureAcronym DescriptionCEchip enableCMOS complement

Seite 22

CY7C1365CDocument Number: 001-74584 Rev. *C Page 29 of 30Document History PageDocument Title: CY7C1365C, 9-Mbit (256 K × 32) Flow-Through Sync SRAMDo

Seite 23

CY7C1365CDocument Number: 001-74584 Rev. *C Page 3 of 30ContentsPin Configurations ...4Pin D

Seite 24

Document Number: 001-74584 Rev. *C Revised October 25, 2012 Page 30 of 30Intel and Pentium are registered trademarks and i486 is a trademark of Intel

Seite 25

CY7C1365CDocument Number: 001-74584 Rev. *C Page 4 of 30Pin ConfigurationsFigure 1. 165-ball FBGA pinoutCY7C1365C (256 K × 32)234 5671ABCDEFGHJKLMNP

Seite 26 - Ordering Code Definitions

CY7C1365CDocument Number: 001-74584 Rev. *C Page 5 of 30Pin DescriptionsName I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select

Seite 27

CY7C1365CDocument Number: 001-74584 Rev. *C Page 6 of 30TDI JTAG serial input synchronousSerial data-in to the JTAG circuit. Sampled on the rising ed

Seite 28 - Units of Measure

CY7C1365CDocument Number: 001-74584 Rev. *C Page 7 of 30Functional OverviewAll synchronous inputs pass through input registers controlled bythe risin

Seite 29

CY7C1365CDocument Number: 001-74584 Rev. *C Page 8 of 30ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max UnitIDDZZSlee

Seite 30 - PSoC Solutions

CY7C1365CDocument Number: 001-74584 Rev. *C Page 9 of 30Truth TableThe truth table for CY7C1365C follows. [1, 2, 3, 4, 5]Cycle Description Address Us

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