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Migrating From EZ-USB FX2™ to EZ-USB FX2LP™

is 50–60 mA max., not meeting the unconfigured current limit

when using the device as bus powered, is no longer an

issue—there is no need to set this control bit in the EEPROM

anymore. The workaround is not required anymore. Just have

the FX2LP application enumerate in USB high-speed mode

from the start.

In order for an FX2 bus powered application that uses double

enumeration sequence to behave the same when replaced

with FX2LP, all you need to do is set the control bit of the

EEPROM to 0 (chirp enabled) and can leave the firmware ‘as

is’ with the double enumeration workaround code in it.

Expanded Code/Data RAM

The FX2LP has 16 Kbytes of internal Code/Data RAM, where

the FX2 had only 8 Kbytes. The additional RAM is located in

the address space of 0x2000 to 0x3FFF. If the firmware of the

existing design is completely internal to the FX2, no changes

are required to use the FX2LP. If the FX2 design had RAM at

this location, no changes are required. The FX2LP will access

the internal RAM instead of the external RAM.

If there was either memory mapped ROM (any non-volatile

memory) or memory mapped I/O within these locations, they

must be mapped to new locations and the firmware should be

relinked. In the limited number of designs that require this

change, just a logic change to a FPGA or programmable logic

array for hardware memory decoding and changing the target

location of the external code within the compiler/linker is

required.

In most designs it is felt that the external memory map would

not have used this location in memory. Less logic is required

to locate the memory at higher locations and therefore it is

believed that most designs would have used a higher

address, such as 0x8000, to start the external memory. If this

is the case, no modifications, other then the required crystal

modifications, are required.

ECC Generation on GPIF Data

This is a new feature and does not affect existing designs. If

ECC generation is to be added to an existing design there are

additional registers that enable this function.

The FX2LP can be configured to either calculate two separate

256-byte ECCs on two consecutive 256-byte blocks of data,

or alternatively one single 512-byte ECC on a 512-byte block

of data. Once the 8051 resets the ECC calculation by writing

any value to ECCRESET, the FX2LP will calculate ECC on

any data bytes that transfer across the GPIF or Slave FIFO

interface. The FX2LP will stop ECC calculation once 512

bytes have been processed and it will wait for a new ECC

reset from the 8051 before it commences any new calcula-

tions.

The additional registers for this function are:

ECCCFG: Configuration register (256/512)

ECCRESET Reset ECC-byte registers to zero

ECC1B0, This is the second eight bits of the line

parity on the first 256-byte block or the

512-byte block.

ECC1B1 Lower eight bits of line parity on first 256-byte

block or lower eight bits of line parity on 512-byte

block.

ECC1B2 This is the 6-bit column parity on first

256-byte block or 6-bit column parity on and

upper two bits of line parity for 512-byte

block.

ECC2B0 This is the second eight bits of the line

parity. on the second 256-byte block

ECC2B1 Lower eight bits of line parity on second

256-byte block

ECC2B2 This is the 6-bit column parity on the second

256-byte block

(For column and line parity see Smartmedia Specification.)

See Technical Reference Manual for check/correct sample

code.

Zero-length in Packets with No Firmware Intervention and

Data PID Sequencing for ISO Transfers

The FX2LP has the capability of sending a zero length isoch-

ronous data packet (ZLP) when the host issues an IN token

to an isochronous IN endpoint FIFO and the SIE does not

have any data packets available.

This feature is very useful when designing high-bandwidth

isochronous applications. When an isochronous IN endpoint

is configured for greater than one packet per microframe,

there is a possibility of the core not having more than one

packet available in a microframe. In this case, when the host

issues an IN token, the FX2LP core will automatically send a

zero length packet with the appropriate data PID. Hence

avoiding the occurrence of a scenario where the host may

encounter a turnaround time-out error on not receiving any

data when requesting more than one packet per microframe.

In version 1.1 of the Technical Reference Manual, registers

EPxISOINPKTS defines an additional bit called: ADDJ. This

bit defaults to a zero value. In this condition, FX2LP operates

the same as the FX2. This bit (AADJ) is a RESERVED bit in

FX2LP and should be left to its default value of 0.

The auto adjust (AADJ) feature was useful when designing

with the FX2LP engineering samples provided at the early

stages of the FX2LP development. These engineering

samples did not have the ability to issue a zero length isoch-

ronous packet automatically and hence were prone to

running into a DATA PID mismatch scenario when dealing

with high bandwidth ISO IN transfer (please refer to the

“Streaming Data Through Isochronous/Bulk Endpoints on

EZ-USB FX2” application note for further information on

DATA PID mismatch issue). The auto adjust feature was a

partial workaround to the data PID mismatch issue and in

order to use this workaround, the wMaxPacketSize that could

be defined in the isochronous endpoint descriptor was limited

to 1024 bytes. The latest (production) version of the FX2LP

is capable of issuing a zero length packet automatically when

there is no data packet available in the core, which resolves

the issue regarding the data PID mismatch. Hence the auto

adjust feature is really not necessary to be used when using

this production version of the FX2LP silicon. This latest

version of the silicon requires that this AADJ bit be left to its

default value of 0 and be treated as a reserved bit. The next

version (after 1.1) of the Technical Reference Manual will

update the usage of this bit to be treated as a reserved bit.

Using this ZLP improvements the part has addressed the

Data PID mismatch issue and using this feature has resulted

in increasing the data throughput tremendously.

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