Cypress Semiconductor Perform nvSRAM Spezifikationen PDF herunterladen (Seite 23)

CY14B256KA

Document Number: 001-55720 Rev. *H Page 23 of 28

Hardware STORE Cycle

Over the Operating Range

Parameter Description Min Max Unit

DHSB

HSB to output active time when write latch not set – 25 ns

PHSB

Hardware STORE pulse width 15 – ns

Switching Waveforms

Figure 15. Hardware STORE Cycle

[40]

Figure 16. Soft Sequence Processing

[41, 42]

PHSB

DELAY

DHSB

DELAY

STORE

HHHD

LZHSB

Write latch set

Write latch not set

HSB (IN)

HSB (OUT)

DQ (Data Out)

RWI

HSB (IN)

HSB (OUT)

RWI

HSB pin is driven high to V

only by Internal

SRAM is disabled as long as HSB (IN) is driven low

HSB driver is disabled

DHSB

100 kOhm resistor,

Address #1 Address #6 Address #1 Address #6

Soft Sequence

Command

Address

Soft Sequence

Command

Notes

40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

41. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

42. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

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