Cypress Semiconductor STK14C88-5 Bedienungsanleitung PDF herunterladen (Seite 13)

STK14C88-5

Document Number: 001-51038 Rev. *B Page 13 of 18

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows.

[22]

Parameter Alt Description

35 ns 45 ns

Unit

Min Max Min Max

[20]

AVAV

STORE/RECALL initiation cycle time 35 – 45 – ns

[21, 22]

AVEL

Address setup time 0 – 0 – ns

[21, 22]

ELEH

Clock pulse width 25 – 30 – ns

HACE

[21, 22]

ELAX

Address hold time 20 – 20 – ns

RECALL

RECALL duration – 20 – 20 s

Switching Waveforms

Figure 13. CE Controlled Software STORE/RECALL Cycle

[22]

SCE

HACE

STORE

/ t

RECALL

DATA VALID

6 # SSERDDA1 # SSERDDA

HIGH IMPEDANCE

ADDRESS

DQ (DATA)

Notes

20. CE

and OE low and WE high for output behavior.

21. The software sequence is clocked on the falling edge of CE

without involving OE (double clocking aborts the sequence).

22. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

1 2 ... 8 9 10 11 12 13 14 15 16 17 18

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