Cypress Semiconductor CY7B9911V Bedienungsanleitung PDF herunterladen (Seite 4)

CY7B9911V

3.3V RoboClock+™

Document #: 38-07408 Rev. *B Page 4 of 12

Operational Mode Descriptions

Figure 2 shows the LVPSCB configured as a zero-skew clock

buffer. In this mode the CY7B9911V can be used as the basis

for a low-skew clock distribution tree. When all of the function

select inputs (xF0, xF1) are left open, the outputs are aligned

and may each drive a terminated transmission line to an

independent load. The FB input can be tied to any output in

this configuration and the operating frequency range is

selected with the FS pin. The low-skew specification, coupled

with the ability to drive terminated transmission lines (with

impedances as low as 50Ω), allows efficient printed circuit

board design.

Figure 3 shows a configuration to equalize skew between

metal traces of different lengths. In addition to low skew

between outputs, the LVPSCB can be programmed to stagger

the timing of its outputs. The four groups of output pairs can

each be programmed to different output timing. Skew timing

can be adjusted over a wide range in small increments with the

appropriate strapping of the function select pins. In this config-

uration the 4Q0 output is fed back to FB and configured for

zero skew. The other three pairs of outputs are programmed

to yield different skews relative to the feedback. By advancing

the clock signal on the longer traces or retarding the clock

signal on shorter traces, all loads can receive the clock pulse

at the same time.

In this illustration the FB input is connected to an output with

0-ns skew (xF1, xF0 = MID) selected. The internal PLL

synchronizes the FB and REF inputs and aligns their rising

edges to insure that all outputs have precise phase alignment.

Clock skews can be advanced by ±6 time units (t

) when using

an output selected for zero skew as the feedback. A wider range of

delays is possible if the output connected to FB is also skewed.

Since “Zero Skew”, +t

, and –t

are defined relative to output

groups, and since the PLL aligns the rising edges of REF and FB,

it is possible to create wider output skews by proper selection of the

xFn inputs. For example a +10 t

between REF and 3Qx can be

achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,

3F0 = MID, and 3F1 = High. (Since FB aligns at –4 t

and 3Qx

Figure 2. Zero-Skew and/or Zero-Delay Clock Driver

SYSTEM

CLOCK

LENGTH L1 = L2 = L3 = L4

REF

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

TEST

LOAD

REF

Figure 3. Programmable-Skew Clock Driver

LENGTH L1 = L2

L3 < L2 by 6 inches

L4 > L2 b

6 inches

SYS-

TEM

CLOCK

REF

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

TEST

LOAD

REF

1 2 3 4 5 6 7 8 9 10 11 12

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