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CY14B101K
1 Mbit (128K x 8) nvSRAM With Real Time Clock
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-06401 Rev. *J Revised November 26, 2009
Features
25 ns, 35 ns, and 45 ns access times
Pin compatible with STK17TA8
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock (RTC)
Low power, 350 nA RTC current
Capacitor or battery backup for RTC
Watchdog timer
Clock alarm with programmable interrupts
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap™ initiated by software, device pin, or
on power down
RECALL to SRAM initiated by software or on power up
Infinite READ, WRITE, and RECALL cycles
High reliability
Endurance to 200K cycles
Data retention: 20 years at 55°C
Single 3V operation with tolerance of +20%, –10%
Commercial and industrial temperature
48-Pin SSOP package (ROHS compliant)
Functional Description
The Cypress CY14B101K combines a 1 Mbit nonvolatile static
RAM with a full featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable high accuracy oscillator.
The alarm function is programmable for one time alarm or
periodic seconds, minutes, hours, or days. There is also a
programmable watchdog timer for process control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
1024 X 1024
QuantumTrap
1024 x 1024
STORE
RECALL
COLUMN IO
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
15
- A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
RTC
MUX
A
16
- A
0
x
1
x
2
INT
V
RTCbat
V
RTCcap
Logic Block Diagram
Not Recommended for New Designs
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Inhaltsverzeichnis

Seite 1 - CY14B101K

CY14B101K1 Mbit (128K x 8) nvSRAM With Real Time ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600D

Seite 2

CY14B101KDocument Number: 001-06401 Rev. *J Page 10 of 29Power MonitorThe CY14B101K provides a power management scheme withpower fail interrupt capabi

Seite 3

CY14B101KDocument Number: 001-06401 Rev. *J Page 11 of 29Figure 5. Interrupt Block DiagramFigure 6. RTC Recommended Component ConfigurationWDF - Wat

Seite 4

CY14B101KDocument Number: 001-06401 Rev. *J Page 12 of 29Table 4. RTC Register Map[5, 6]RegisterBCD Format Data [5]Function/RangeD7 D6 D5 D4 D3 D2 D1

Seite 5 - Noise Considerations

CY14B101KDocument Number: 001-06401 Rev. *J Page 13 of 29Table 5. Register Map Detail0x1FFFFTime Keeping - YearsD7 D6 D5 D4 D3 D2 D1 D010s Years Year

Seite 6 - Best Practices

CY14B101KDocument Number: 001-06401 Rev. *J Page 14 of 290X1FFF8Calibration/ControlD7 D6 D5 D4 D3 D2 D1 D0OSCEN 0 CalibrationSignCalibrationOSCEN Osci

Seite 7

CY14B101KDocument Number: 001-06401 Rev. *J Page 15 of 290x1FFF4Alarm - HoursD7 D6 D5 D4 D3 D2 D1 D0M 10s Alarm Hours Alarm HoursContains the alarm va

Seite 8

CY14B101KDocument Number: 001-06401 Rev. *J Page 16 of 29Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These user

Seite 9 - Watchdog Timer

CY14B101KDocument Number: 001-06401 Rev. *J Page 17 of 29Data Retention and EnduranceParameter Description Min UnitDATARData Retention 20 YearsNVCNonv

Seite 10

CY14B101KDocument Number: 001-06401 Rev. *J Page 18 of 29AC Switching Characteristics ParameterDescription25 ns 35 ns 45 nsUnitMin Max Min Max Min Max

Seite 11

CY14B101KDocument Number: 001-06401 Rev. *J Page 19 of 29AC Switching Characteristics (continued)ParameterDescription25 ns 35 ns 45 nsUnitMin Max Min

Seite 12

CY14B101KDocument Number: 001-06401 Rev. *J Page 2 of 29ContentsFeatures ...

Seite 13

CY14B101KDocument Number: 001-06401 Rev. *J Page 20 of 29AutoStore or Power Up RECALLParameter DescriptionCY14B101KUnitMin MaxtHRECALL [18]Power Up RE

Seite 14

CY14B101KDocument Number: 001-06401 Rev. *J Page 21 of 29Software Controlled STORE/RECALL Cycles [21, 22]ParameterAlt. ParameterDescription25 ns 35 n

Seite 15

CY14B101KDocument Number: 001-06401 Rev. *J Page 22 of 29Hardware STORE CycleParameterAlt. ParameterDescriptionCY14B101KUnitMin MaxtDELAY [25]Time All

Seite 16

CY14B101KDocument Number: 001-06401 Rev. *J Page 23 of 29RTC CharacteristicsParameter Description Test Conditions Min Max UnitIBAK [26]RTC Backup Curr

Seite 17

CY14B101KDocument Number: 001-06401 Rev. *J Page 24 of 29Part Numbering NomenclatureOption:T - Tape and ReelBlank - Std.Speed:25 - 25 nsData Bus:K - x

Seite 18

CY14B101KDocument Number: 001-06401 Rev. *J Page 25 of 29Ordering InformationThese parts are not recommended for new designs.Speed(ns)Ordering CodePac

Seite 19

CY14B101KDocument Number: 001-06401 Rev. *J Page 26 of 29Package DiagramsFigure 17. 48-Pin Shrunk Small Outline Package (51-85061)51-85061-*CNot Reco

Seite 20

CY14B101KDocument Number: 001-06401 Rev. *J Page 27 of 29Document History PageDocument Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock

Seite 21

CY14B101KDocument Number: 001-06401 Rev. *J Page 28 of 29*I 2663934 GVCH/PYRS 02/24/09 Updated FeaturesUpdated pin definition of WE Removed AutoStore

Seite 22

Document Number: 001-06401 Rev. *J Revised November 26, 2009 Page 29 of 29AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor

Seite 23

CY14B101KDocument Number: 001-06401 Rev. *J Page 3 of 29Pin ConfigurationsFigure 1. 48-Pin SSOPTable 1. Pin DefinitionsPin Name Alt I/O Type Descrip

Seite 24

CY14B101KDocument Number: 001-06401 Rev. *J Page 4 of 29Device OperationThe CY14B101K nvSRAM consists of two functional compo-nents paired in the same

Seite 25

CY14B101KDocument Number: 001-06401 Rev. *J Page 5 of 29SRAM READ and WRITE operations that are in progress whenHSB is driven LOW by any means are giv

Seite 26

CY14B101KDocument Number: 001-06401 Rev. *J Page 6 of 29Low Average Active PowerCMOS technology provides the CY14B101K the benefit ofdrawing significa

Seite 27

CY14B101KDocument Number: 001-06401 Rev. *J Page 7 of 29Table 2. Mode SelectionCE WE OEA15 – A0 Mode I/O PowerH X X X Not Selected Output High Z Stan

Seite 28

CY14B101KDocument Number: 001-06401 Rev. *J Page 8 of 29Real Time Clock OperationnvTIME OperationThe CY14B101K offers internal registers that contain

Seite 29 - Products

CY14B101KDocument Number: 001-06401 Rev. *J Page 9 of 29Calibrating the ClockThe RTC is driven by a quartz controlled oscillator with a nominalfrequen

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