Cypress Semiconductor CY14B101K Spezifikationen PDF herunterladen (Seite 18)

CY14B101K

Document Number: 001-06401 Rev. *J Page 18 of 29

AC Switching Characteristics

Parameter

Description

25 ns 35 ns 45 ns

Unit

Min Max Min Max Min Max

Cypress

Parameter

Alt.

Parameter

SRAM Read Cycle

ACE

ELQV

Chip Enable Access Time 25 35 45 ns

[11]

AVAV,

ELEH

Read Cycle Time 25 35 45 ns

[12]

AVQV

Address Access Time 25 35 45 ns

DOE

GLQV

Output Enable to Data Valid 12 15 20 ns

OHA

[12]

AXQX

Output Hold After Address Change 3 3 3 ns

LZCE

[13]

ELQX

Chip Enable to Output Active 3 3 3 ns

HZCE

[13]

EHQZ

Chip Disable to Output Inactive 10 13 15 ns

LZOE

[13]

GLQX

Output Enable to Output Active 0 0 0 ns

HZOE

[13]

GHQZ

Output Disable to Output Inactive 10 13 15 ns

[14]

ELICCH

Chip Enable to Power Active 0 0 0 ns

[14]

EHICCL

Chip Disable to Power Standby 25 35 45 ns

Figure 8. SRAM Read Cycle 1: Address Controlled

[11, 12, 15]

Figure 9. SRAM Read Cycle 2: CE and OE Controlled

[11, 15]

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Notes

11. WE

is HIGH during SRAM Read Cycles.

12. Device is continuously selected with CE and OE both Low.

13. Measured ±200 mV from steady state output voltage.

14. These parameters are guaranteed by design and are not tested.

15. HSB

must remain HIGH during READ and WRITE cycles.

Not Recommended for New Designs

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