Cypress Semiconductor enCoRe CY7C64215 Bedienungsanleitung PDF herunterladen

August 17, 2011 Document No. 001-15340 Rev. *A 1

Migrating Designs from CY7C64x13

to CY7C64215 (enCoRe™ III)

Abstract

AN6073 describes the differences and similarities between Cypress’s CY7C64x13 and CY7C64215 full-speed USB microcon-

trollers with the intent of guiding customers when migrating designs from the CY7C64x13 to the new generation CY7C64215

microcontroller.

Introduction

Cypress Semiconductor highly recommends that its new gen-

eration enCoRe™ III (CY7C64215) be used for new full-

speed USB peripheral designs instead of the legacy

CY7C64x13. Customers who are currently designed in with

the CY7C64x13 are encouraged to migrate to new designs

with the CY7C64215. The reasoning behind this is that, at a

higher level, enCoRe III has the following enhancements over

CY7C64x13:

■ Faster/better performance (processing speed)

■ Broader operating voltage range

■ Larger on-chip memories (FLASH and RAM)

■ enCoRe III is in-system programmable and

reprogrammable

■ Improved Serial Interface Engine (SIE)

Also, as the device name implies (enCoRe – enhanced com-

ponent reduction) it integrates many of the components nor-

mally required by a USB microcontroller, thus leading to lower

system Bill of Materials (BOM) costs. Some of the features

integrated are:

■ Internal Oscillators – Main Oscillator and Low-Power os-

cillator for sleep timer functions

■ Internal regulator – 3.3 V with integrated pull-up resistor

■ System Resources like I2C, user-configurable low-voltage

detection, voltage reference etc.

■ User configurable functions (predefined and available as

modules)

The enCoRe III also uses contemporary development/emula-

tion tools, which makes development easier.

This application note highlights the similarities and differ-

ences between Cypress full-speed USB microcon-

trollers—the CY7C64x13C microcontroller and enCoRe

III—and serves as a guide book when migrating designs from

CY7C64x13 to CY7C64215. This application note assumes

that the reader is familiar with USB fundamentals and the leg-

acy Cypress CY7C64x13 microcontroller.

Features and Architecture of the Two

Microcontrollers

CY7C64x13 Microcontroller

The CY7C64x13 is an 8-bit full-speed USB microcontroller

that follows the Harvard architecture with USB optimized

instructions. It requires an external 6 MHz crystal for opera-

tion and is capable of providing a 12 MHz internal CPU clock

and a 48 MHz internal clock as well.

The device has a PROM-based 8-KB program memory and

256 bytes of SRAM for stack and data variables. It has four

GPIO ports with maskable interrupts on all pins. Ports 0,1 and

2 are capable of sinking 7 mA per pin and port 3 can sink up

to 12 mA per pin. Each GPIO port can be configured as

inputs with internal pull ups, open drain outputs or traditional

CMOS outputs. A DAC port with programmable current sink

outputs is available on the CY7C64113.

The CY7C64x13 has an integrated Master/Slave I

C-compat-

ible Controller (100 kHz) enabled through General-Purpose

I/O (GPIO) pins and an integrated Hardware Assisted Parallel

Interface (HAPI) for data transfer to external devices. Also

integrated in the device is a 12-bit free-running timer with

1-μs clock ticks, a watchdog timer, and internal power on

reset.

AN6073

Author: Jacob Tomy

Associated Project: No

Associated Part Family: CY7C64215

Associated Application Notes: None

1 2 3 4 5 6 ... 15 16

Inhaltsverzeichnis

Seite 1 - Microcontrollers

August 17, 2011 Document No. 001-15340 Rev. *A 1 Migrating Designs from CY7C64x13to CY7C64215 (enCoRe™ III)Abstract AN6073 describes the differences

Seite 2 - Logic Block Diagram

August 17, 2011 Document No. 001-15340 Rev. *AAN6073104. Write to the sleep bit of the CPU_SCR register. This pow-ers down most of the PSoC systems in

Seite 3

August 17, 2011 Document No. 001-15340 Rev. *AAN607311Building a 1-ms Timer using Resources on the CY7C64215One common method is using an 8-bit PWM us

Seite 4

August 17, 2011 Document No. 001-15340 Rev. *AAN607312AppendixAssembler Instruction Differences between M8B and M8C Processor CoresThere are differenc

Seite 5 - Memory Organization

August 17, 2011 Document No. 001-15340 Rev. *AAN60731327 DEC [expr] 7 DEC M[k] 7 7A 028 DEC [X+expr] 8 DEC M[X+k] 8 7B 029 IORD expr 5 MOV A, I

Seite 6 - Interrupts

August 17, 2011 Document No. 001-15340 Rev. *AAN607314New Instructions in M8CThe larger ROM size in M8C allows for many more instruc-tions. The additi

Seite 7 - Watchdog

August 17, 2011 Document No. 001-15340 Rev. *AAN607315About the Author ADD SP,i 5 38 ASR M[k] 7 68CMP M[k],i 8 3C ASR M[X+k] 8 69CMP M[X+k],i 9 3D RLC

Seite 8 - Voltage Regulator

AN6073Cypress Semiconductor198 Champion CourtSan Jose, CA 95134-1709Phone: 408-943-2600Fax: 408-943-4730http://www.cypress.com© Cypress Semiconductor

Seite 9 - Suspend Condition

August 17, 2011 Document No. 001-15340 Rev. *AAN60732The CY7C64x13 has an integrated transceiver and can support five user configured endpoints—up to

Seite 10 - CY7C64215 Microcontroller

August 17, 2011 Document No. 001-15340 Rev. *AAN60733protection modes available. It has a 1K SRAM for data vari-ables and stack.The device has an inte

Seite 11

August 17, 2011 Document No. 001-15340 Rev. *AAN60734Differences Between the Two Microcontrollers Features/Characteristics CY7C64x13 CY7C64215CPU core

Seite 12 - Appendix

August 17, 2011 Document No. 001-15340 Rev. *AAN60735ClockingThe CY7C64x13 microcontroller requires an external crystalor an external clock for operat

Seite 13

August 17, 2011 Document No. 001-15340 Rev. *AAN60736Figure 4. enCoRe III Stack/SRAM Setup enCoRe III has 16 KB of FLASH, 1K SRAM for user variablesa

Seite 14 - New Instructions in M8C

August 17, 2011 Document No. 001-15340 Rev. *AAN60737The CY7C64215 CPU uses an interrupt controller with up to20 vectors. Flash locations 00h to 2Ch a

Seite 15 - About the Author

August 17, 2011 Document No. 001-15340 Rev. *AAN60738[4:3] of the OSC_CR0 register and can range from 6 ms to3s, depending on the value written.Sleep

Seite 16 - Document History Page

August 17, 2011 Document No. 001-15340 Rev. *AAN60739USB BootloaderenCoRe III supports in-system programmability. This, how-ever, requires that the ch