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10.4 Data Memory Write

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 will only be active while

either RD# or WR# are active. The address of AUTOPTR2 will be active throughout the cycle and meet the above address valid

time for which is based on the stretch value.

OFF1

CLKOUT

A[15..0]

WR#

D[7..0]

STBL

STBH

data out

OFF1

CLKOUT

A[15..0]

WR#

D[7..0]

data out

Stretch = 1

ON1

SCSL

CS#

ON1

CS#

Figure 10-3. Data Memory Write Timing Diagram

Table 10-3. Data Memory Write Parameters

Parameter Description Min. Max. Unit Notes

Delay from Clock to Valid Address 0 10.7 ns

STBL

Clock to WR Pulse LOW 0 11.2 ns

STBH

Clock to WR Pulse HIGH 0 11.2 ns

SCSL

Clock to CS Pulse LOW 13.0 ns

ON1

Clock to Data Turn-on 0 13.1 ns

OFF1

Clock to Data Hold Time 0 13.1 ns

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 59 60

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Cypress Semiconductor FX2LP Bedienungsanleitung Seite 40