Cypress Semiconductor FX2LP Bedienungsanleitung PDF herunterladen (Seite 46)

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10.10 Slave FIFO Asynchronous Write

10.11 Slave FIFO Synchronous Packet End Strobe

There is no specific timing requirement that needs to be met

for asserting PKTEND pin with regards to asserting SLWR.

PKTEND can be asserted with the last data value clocked into

the FIFOs or thereafter. The only consideration is the set-up

time t

SPE

and the hold time t

PEH

must be met.

Although there are no specific timing requirements for the

PKTEND assertion, there is a specific corner case condition

that needs attention while using the PKTEND to commit a one

byte/word packet. There is an additional timing requirement

that need to be met when the FIFO is configured to operate in

DATA

SFD

FDH

FLAGS

XFD

SLWR/SLCS#

WRpwh

WRpwl

Figure 10-10. Slave FIFO Asynchronous Write Timing Diagram

[20]

SLWR

Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK

[23]

Parameter Description Min. Max. Unit

WRpwl

SLWR Pulse LOW 50 ns

WRpwh

SLWR Pulse HIGH 70 ns

SFD

SLWR to FIFO DATA Set-up Time 10 ns

FDH

FIFO DATA to SLWR Hold Time 10 ns

XFD

SLWR to FLAGS Output Propagation Delay 70 ns

FLAGS

XFLG

IFCLK

PKTEND

SPE

PEH

Figure 10-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram

[20]

Table 10-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK

[21]

Parameter Description Min. Max. Unit

IFCLK

IFCLK Period 20.83 ns

SPE

PKTEND to Clock Set-up Time 14.6 ns

PEH

Clock to PKTEND Hold Time 0 ns

XFLG

Clock to FLAGS Output Propagation Delay 9.5 ns

Table 10-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK

[21]

Parameter Description Min. Max. Unit

IFCLK

IFCLK Period 20.83 200 ns

SPE

PKTEND to Clock Set-up Time 8.6 ns

PEH

Clock to PKTEND Hold Time 2.5 ns

XFLG

Clock to FLAGS Output Propagation Delay 13.5 ns

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 59 60

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