Cypress Semiconductor FX2LP Bedienungsanleitung PDF herunterladen (Seite 43)

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10.7 Slave FIFO Synchronous Read

IFCLK

SLRD

FLAGS

SLOE

SRD

RDH

OEon

XFD

XFLG

DATA

IFCLK

N+1

OEoff

Figure 10-7. Slave FIFO Synchronous Read Timing Diagram

[20]

Table 10-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK

[21]

Parameter Description Min. Max. Unit

IFCLK

IFCLK Period 20.83 ns

SRD

SLRD to Clock Set-up Time 18.7 ns

RDH

Clock to SLRD Hold Time 0 ns

OEon

SLOE Turn-on to FIFO Data Valid 10.5 ns

OEoff

SLOE Turn-off to FIFO Data Hold 10.5 ns

XFLG

Clock to FLAGS Output Propagation Delay 9.5 ns

XFD

Clock to FIFO Data Output Propagation Delay 11 ns

Table 10-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK

[21]

Parameter Description Min. Max. Unit

IFCLK

IFCLK Period 20.83 200 ns

SRD

SLRD to Clock Set-up Time 12.7 ns

RDH

Clock to SLRD Hold Time 3.7 ns

OEon

SLOE Turn-on to FIFO Data Valid 10.5 ns

OEoff

SLOE Turn-off to FIFO Data Hold 10.5 ns

XFLG

Clock to FLAGS Output Propagation Delay 13.5 ns

XFD

Clock to FIFO Data Output Propagation Delay 15 ns

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 59 60

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