
CY7C1361V25
CY7C1363V25
CY7C1365V25
PRELIMINARY
25
Timing Diagrams
(continued)
Pipeline Timing
t
AS
= DON’T CARE
= UNDEFINED
t
CLZ
t
CHZ
t
DOH
CLK
ADD
WE
CE
1
Data In/Out
ADSC
ADSP
ADV
CE
OE
D(C)
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
CEH
t
CES
t
WEH
t
WES
t
CDV
ADSP ignored
with CE
1
HIGH
RD1 RD2 RD3 RD4
WD1 WD2 WD3 WD4
1a
Out
2a
Out
3a
Out
4a
Out
1a
In
2a
In
3a
In
4a
In
Back to Back Reads
ADSP initiated Reads
ADSC initiated Reads
Back to Back Writes
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