Cypress Semiconductor CY7C1386F Bedienungsanleitung PDF herunterladen (Seite 11)

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *H Page 11 of 36

Truth Table

The Truth Table for CY7C1386D, CY7C1386F, CY7C1387D, and CY7C1387F follow.

[6, 7, 8, 9, 10]

Operation Add. Used CE

ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect cycle, power-down None H X X L X L X X X L–H Tristate

Deselect cycle, power-down None L L X L L X X X X L–H Tristate

Deselect cycle, power-down None L X H L L X X X X L–H Tristate

Deselect cycle, power-down None L L X L H L X X X L–H Tristate

Deselect cycle, power-down None L X H L H L X X X L–H Tristate

Sleep mode, power-down None X X X H X X X X X X Tristate

Read cycle, begin burst External L H L L L X X X L L–H Q

Read cycle, begin burst External L H L L L X X X H L–H Tristate

Write cycle, begin burst External L H L L H L X L X L–H D

Read cycle, begin burst External L H L L H L X H L L–H Q

Read cycle, begin burst External L H L L H L X H H L–H Tristate

Read cycle, continue burst Next X X X L H H L H L L–H Q

Read cycle, continue burst Next X X X L H H L H H L–H Tristate

Read cycle, continue burst Next H X X L X H L H L L–H Q

Read cycle, continue burst Next H X X L X H L H H L–H Tristate

Write cycle, continue burst Next X X X L H H L L X L–H D

Write cycle, continue burst Next H X X L X H L L X L–H D

Read cycle, suspend burst Current X X X L H H H H L L–H Q

Read cycle, suspend burst Current X X X L H HHHHL–HTristate

Read cycle, suspend burst Current H X X L X H H H L L–H Q

Read cycle, suspend burst Current H X X L X HHHHL–HTristate

Write cycle, suspend burst Current X X X L H H H L X L–H D

Write cycle, suspend burst Current H X X L X H H L X L–H D

Notes

6. X = Do not care, H = Logic HIGH, L = Logic LOW.

7. WRITE

= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

8. The DQ pins are controlled by the current cycle and the OE

signal. OE is asynchronous and is not sampled with the clock.

9. The SRAM always initiates a read cycle when ADSP

is asserted, regardless of the state of GW, BWE, or BW

. Writes may occur only on subsequent clocks after

the ADSP

or with the assertion of

ADSC

. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care

for the remainder of the write cycle.

10. OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive

or when the device is deselected, and all data bits behave as output when OE

is active (LOW).

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