Cypress Semiconductor CY7C1386F Bedienungsanleitung PDF herunterladen (Seite 24)

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *H Page 24 of 36

Switching Characteristics

Over the Operating Range

Parameter

[24, 25]

Description

-250 -200 -167

Unit

Min Max Min Max Min Max

POWER

(Typical) to the first access

[26]

1–1–1–ms

Clock

CYC

Clock cycle time 4.0 – 5.0 – 6.0 – ns

Clock HIGH 1.7 – 2.0 – 2.2 – ns

Clock LOW 1.7 – 2.0 – 2.2 – ns

Output Times

Data output valid after CLK rise – 2.6 – 3.0 – 3.4 ns

DOH

Data output hold after CLK rise 1.0 – 1.3 – 1.3 – ns

CLZ

Clock to low Z

[27, 28, 29]

1.0–1.3–1.3–ns

CHZ

Clock to high Z

[27, 28, 29]

– 2.6 – 3.0 – 3.4 ns

OEV

OE LOW to output valid – 2.6 – 3.0 – 3.4 ns

OELZ

OE LOW to output low Z

[27, 28, 29]

0–0–0–ns

OEHZ

OE HIGH to output high Z

[27, 28, 29]

– 2.6 – 3.0 – 3.4 ns

Setup Times

Address setup before CLK rise 1.2 – 1.4 – 1.5 – ns

ADS

ADSC, ADSP setup before CLK rise 1.2 – 1.4 – 1.5 – ns

ADVS

ADV setup before CLK rise 1.2 – 1.4 – 1.5 – ns

WES

GW, BWE, BW

setup before CLK

rise

1.2–1.4–1.5–ns

Data input setup before CLK rise 1.2 – 1.4 – 1.5 – ns

CES

Chip enable setup before CLK rise 1.2 – 1.4 – 1.5 – ns

Hold Times

Address hold after CLK rise 0.3 – 0.4 – 0.5 – ns

ADH

ADSP, ADSC hold after CLK rise 0.3 – 0.4 – 0.5 – ns

ADVH

ADV hold after CLK rise 0.3 – 0.4 – 0.5 – ns

WEH

GW, BWE, BW

hold after CLK rise0.3–0.4–0.5–ns

Data input hold after CLK rise 0.3 – 0.4 – 0.5 – ns

CEH

Chip enable hold after CLK rise 0.3 – 0.4 – 0.5 – ns

Notes

24. Timing reference level is 1.5 V when V

DDQ

= 3.3 V and is 1.25 V when V

DDQ

= 2.5 V.

25. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted.

26. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

(minimum) initially before a read or write operation can

be initiated.

27. t

CHZ

, t

CLZ

OELZ

, and t

OEHZ

are specified with AC test conditions shown in (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage.

28. At any voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same data bus.

These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z

prior to low Z under the same system conditions.

29. This parameter is sampled and not 100% tested.

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