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3.2 Interfacing USB controller and DSP chip

Figure 2: CPLD connections

The Endpoint buffers for the USB controller chip are implemented as FIFOs. Access to

the endpoint buffers can be achieved by the CPU in two ways.

1) As Ram Blocks

2) As a FIFO

However to optimize the data transfer rates it is essential that the CPU should not

interfere and hence should be accesed as a FIFO. The FIFO is directly accessible to

external peripherals and can be accessed in two ways.

1) Using GPIF (general purpose interface) with the USB controller acting as the master

for the transfers.

2) Using the FIFO as Slave FIFOs and the DSP acting as the master for the transfers.

The use of GPIF requires the DSP to follow cypress controller CLKOUT for

synchronization. However the DSP allows external peripherals to synchronize using its

own clock. Hence the USB controller FIFOs must be used as slaves.

1) Serially

2) Using the primary memory Bus

3) Using the expansion Bus

For good throughput it becomes essential to use one of the buses. The primary bus is used

for ease of implementation. 16 Data lines of DSP chip are connected to 16 data lines of

the controller chip (Port B and Port D) to exchange data between the two chips. The

synchronizing clock is provided by DSP at 75 MHz. The slave FIFOs can handle a

synchronizing clock in the range of 5-48 MHz. This makes it essential for a CPLD to

divide the frequency by a factor of 2 and also correlate the handshake signals on both

sides.

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Cypress Semiconductor CY7C68013A Bedienungsanleitung Seite 3