Cypress Semiconductor CY7C68013A Bedienungsanleitung PDF herunterladen (Seite 5)

The predefined functions were modified to match with the new design however

maintaining the basic structure for compatibility.

For the host side programs to use libusb functions(like bulkwrite and read), a device

handler has to be passed to the code. The source code for the same has been written

4.2 Cypress Firmware

The cypress firmware performs polling of the EP2CS register to check whether the out

endpoint is not empty and also checks using EP6CS whether the in endpoint is not full.

When the above condition is satisfied, the polling is stopped and the command written

into the firmware is interpreted. The commands written to the controller are

RESET VC33, READ _VC33 or SEND_TO_VC33.

4.3 CPLD (Complex Programmable Logic device)

The CPLD has to perform the following functions.

1) Divide the H1 clock of DSP by 2 and provide it as an input to the Controller Slave

FIFO interface.

2) Generate the Read / Write signals for the USB controller (SLRD), (SLWR)

considering the input signal from the DSP.

3) Generate the Ready signal for the DSP from the full/empty flags.

The following logic for the same has been implemented in VHDL.

1) IFCLK = H1/2

2) RDY/ = A or B

where A= FLAGA or (SLRD)

B= FLAGB or (SLWR)

3) SLOE=Page0/ or (not (RD/W))

4) SLRD=not (SLOE) and (IFCLK/2)

5) SLWR=Page0/ or (RD/W)

6) SLCS=0

7) PKTEND =XF0;

8) The address lines of the DSP, A8-15 are checked for addresses 0x10 and 0x11. For this

the out buffer is read by generating 00 on the FIFO address lines.

For the addresses 0x12 write operation is performed & hence the in buffer is selected by

generating the address 01 on the FIFO address lines.

1 2 3 4 5 6 7 8 9

Keine Kommentare

Cypress Semiconductor CY7C68013A Bedienungsanleitung Seite 5