
Document #: 38-05445 Rev. *H Page 11 of 17
Truth Table
CE
1
CE
2
WE OE BHE BLE Inputs/Outputs Mode Power
H X
[29]
X X X X High-Z Deselect/power down Standby (I
SB
)
X
[29]
L X X X X High-Z Deselect/power down Standby (I
SB
)
X
[29]
X
[29]
X X H H High-Z Deselect/power down Standby (I
SB
)
L H H L L L Data Out (I/O
0
–I/O
15
) Read Active (I
CC
)
L H H L H L Data Out (I/O
0
–I/O
7
);
High-Z (I/O
8
–I/O
15
)
Read Active (I
CC
)
L H H L L H High-Z (I/O
0
–I/O
7
);
Data Out (I/O
8
–I/O
15
)
Read Active (I
CC
)
L H H H L H High-Z Output disabled Active (I
CC
)
L H H H H L High-Z Output disabled Active (I
CC
)
L H H H L L High-Z Output disabled Active (I
CC
)
L H L X L L Data In (I/O
0
–I/O
15
) Write Active (I
CC
)
L H L X H L Data In (I/O
0
–I/O
7
);
High-Z (I/O
8
–I/O
15
)
Write Active (I
CC
)
L H L X L H High-Z (I/O
0
–I/O
7
);
Data In (I/O
8
–I/O
15
)
Write Active (I
CC
)
Note
29. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted
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