Cypress Semiconductor NoBL CY7C1472V33 Betriebsanweisung PDF herunterladen (Seite 13)

ZestSC1 User Guide

CONFIDENTIAL Page 13 of 57

The GPIF also has 6 Ready input signals and 6 Control output signals for general purpose

use, and these are all connected to the FPGA. CTL3 and 4 are connected to FPGA

configuration CS_n and WRITE_n. These configuration signals are also connected to Port

C bits 0 & 1, but for high speed configuration the GPIF Control signals are used. In Slave

FIFO mode some of the Ready and Control signals become FIFO control signals. See table

above for Port A signals and table below for Ready and Control signals that are used in

Slave FIFO mode.

GPIF Mode Slave FIFO Mode

RDY0 (I) SLRD – slave read (I)

RDY1 (I) SLWR – slave write (I)

RDY2 (I)

RDY3 (I)

RDY4 (I)

RDY5 (I)

CTL0 (O) FLAG A (O)

CTL1 (O) FLAG B (O)

CTL2 (O) FLAG C (O)

CTL3 (O)

CTL4 (O)

CTL5 (O)

(I) means FX2 input and (O) means FX2 output

7.1.1 Communications with Host

The FPGA uses five means of communication with the FX2 and hence the host computer.

• GPIF mode is used for bulk transfers of FPGA configuration/readback data.

Configuration/readback transfers require two endpoints, one for writing and one

for reading, making a total of two endpoints. The GPIF has a maximum of four

programmable waveforms in its state machine.

• Slave FIFO mode is used for bulk transfers of application data. Application data

transfers require two endpoints, one for writing and one for reading, making a

total of two endpoints. Transfers using the slave FIFO must be a multiple of 512

bytes in length.

• The 8051 external memory interface is used for access to application registers

within the FPGA.

• The 8 bits of Port C of the 8051 are used as general purpose, bi-directional pins.

The use of these pins is determined by the user application. They can be used as

a simple handshaking protocol, state reporting to the host, control from the host

or for any other purpose.

• There is a single interrupt line from the FPGA to the FX2 to allow the FPGA to

interrupt the host PC.

See the references [1], [2], [3], [4] and [5] for details on GPIF mode and Slave FIFO

mode.

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