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ZestSC1 User Guide

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10 Examples

The ZestSC1 Support package contains a number of examples to illustrate the use of the

ZestSC1 and its Host Support Library. The examples are located in the Examples sub-

directory of the ZestSC1 installation directory. Each example consists of a host program

and a Xilinx XST VHDL or Verilog project.

Examples 2 and 4 also contain ModelSim testbenches to illustrate how the various

interfaces can be simulated before implementation.

Example1 shows how to configure the FPGA from a .bit file generated by the Xilinx place

and route tools. The .bit file flashes the LEDs on the board in sequence.

Example2 shows how to use the high-speed streaming interface on the ZestSC1 by

measuring data transfer rates between the FPGA and the host in either direction. The

VHDL/Verilog code implements an infinite data sink and an infinite data source to

illustrate use of the VHDL/Verilog support library.

Example3 shows how to use the low-speed control interface on the ZestSC1 by reading

and writing a memory-mapped register and reading and writing the single bit signals.

The VHDL/Verilog code implements a number of read/write registers and a loop-back of 4

input signals to 4 output signals.

Example4 shows how to use the SRAM on the ZestSC1. The VHDL/Verilog code

implements a DMA engine between the USB streaming port and the SRAM allowing the

host to read and write blocks of data.

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Cypress Semiconductor NoBL CY7C1472V33 Betriebsanweisung Seite 27