Cypress Semiconductor NoBL CY7C1472V33 Betriebsanweisung PDF herunterladen (Seite 19)

ZestSC1 User Guide

CONFIDENTIAL Page 19 of 57

USER_SRAM_A: in std_logic_vector(22 downto 0); -- 23-bit address

USER_SRAM_W: in std_logic; -- write strobe active

-- high

USER_SRAM_R: in std_logic; -- read strobe active

-- high

USER_SRAM_DR_VALID: out std_logic; -- read data valid strobe

-- active high

USER_SRAM_DW: in std_logic_vector(17 downto 0); -- 18-bit data bus for

-- writing to SRAM

USER_SRAM_DR: out std_logic_vector(17 downto 0); -- 18-bit data bus for

-- reading from SRAM

Or, in Verilog:

input [22:0] USER_SRAM_A, // 23-bit address

input USER_SRAM_W, // write strobe active

// high

input USER_SRAM_R, // read strobe active

// high

output USER_SRAM_DR_VALID, // read data valid strobe

// active high

input [17:0] USER_SRAM_DW, // 18-bit data bus for

// writing to SRAM

output [17:0] USER_SRAM_DR // 18-bit data bus for

// reading from SRAM

The Pipelined ZBT SRAM device takes 2 clock cycles for a write and 2 clock cycles for a

read. This logic core has one extra pipeline stage in the write path (giving 3 clock cycles)

and two extra pipeline stages in the read path (giving 4 clock cycles). Figure 7 shows the

signal waveforms at the user interface.

Figure 7. ZBT SRAM Write and Read Cycles

For write cycles the user logic drives the write strobe high and the write address and data

in the same clock cycle. The logic core registers all command and data signals and delays

USER CL

USER SRAM A

USER SRAM W

USER SRAM R

USER SRAM DW

WRITE

READ

USER SRAM DR VALID

USER SRAM D

DAT

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Cypress Semiconductor NoBL CY7C1472V33 Betriebsanweisung Seite 19