Cypress Semiconductor Perform CY7C1380D Bedienungsanleitung PDF herunterladen (Seite 13)

CY7C1380D, CY7C1380F

CY7C1382D, CY7C1382F

Document #: 38-05543 Rev. *E Page 13 of 30

When this scan cell, called the “extest output bus tri-state,” is

latched into the preload register during the Update-DR state in

the TAP controller, it will directly control the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it will enable the output buffers to

drive the output bus. When LOW, this bit will place the output

bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the Shift-DR state. During Update-DR, the value

loaded into that shift-register cell will latch into the preload

directly control the output Q-bus pins. Note that this bit is

preset HIGH to enable the output when the device is powered

up, and also when the TAP controller is in the Test-Logic-Reset

state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

TAP Timing

TAP AC Switching Characteristics

Over the Operating Range

[10, 11]

Parameter Description Min. Max. Unit

Clock

TCYC

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH time 20 ns

TCK Clock LOW time 20 ns

Output Times

TDOV

TCK Clock LOW to TDO Valid 10 ns

TDOX

TCK Clock LOW to TDO Invalid 0 ns

Setup Times

TMSS

TMS Setup to TCK Clock Rise 5 ns

TDIS

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

TMSH

TMS Hold after TCK Clock Rise 5 ns

TDIH

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

Test Clock

(TCK)

Test Mode Select

(TMS)

Test Data-Out

(TDO)

CYC

Test Data-In

(TDI)

TMSH

TMSS

TDIH

TDIS

TDOX

TDOV

DON’T CARE UNDEFINED

Notes:

10. t

and t

refer to the setup and hold time requirements of latching data from the boundary scan register.

11. Test conditions are specified using the load in TAP AC test conditions. t

= 1ns.

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