Cypress Semiconductor Perform CY7C1380D Bedienungsanleitung PDF herunterladen (Seite 23)

CY7C1380D, CY7C1380F

CY7C1382D, CY7C1382F

Document #: 38-05543 Rev. *E Page 23 of 30

Read/Write Cycle Timing

[26, 28, 29]

Switching Waveforms (continued)

CYC

CLK

ADSP

ADH

ADS

ADDRESS

ADSC

CEH

CES

BWE,

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1)

Q(A4) Q(A4+1) Q(A4+2)

WEH

WES

Q(A4+3)

OEHZ

OELZ

CLZ

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

Notes:

28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP

or ADSC.

29. GW

is HIGH.

[+] Feedback

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 29 30

CY7C1380D, CY7C1380F 1
CY7C1382D, CY7C1382F 1
(512K x 36) 2
(1M x 18) 2
Pin Configurations 3
CY7C1382F (1M x 18) 4
CY7C1380F (512K x 36) 4
CY7C1380D (512K x 36) 5
CY7C1382D (1M x 18) 5

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