Cypress Semiconductor Perform STK14D88 Bedienungsanleitung PDF herunterladen (Seite 13)

CY14B256L

Document Number: 001-06422 Rev. *I Page 13 of 19

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows.

[15, 16]

Parameter Alt Description

25 ns 35 ns 45 ns

Unit

Min Max Min Max Min Max

[16]

AVAV

STORE/RECALL Initiation Cycle Time 25 35 45 ns

AVEL

Address Setup Time 0 0 0 ns

ELEH

Clock Pulse Width 20 25 30 ns

GHAX,

ELAX

Address Hold Time 1 1 1 ns

RECALL

RECALL Duration 120 120 120

Switching Waveforms

Figure 10. CE Controlled Software STORE/RECALL Cycle

[16]

Figure 11. OE Controlled Software STORE/RECALL Cycle

[16]

SCE

STORE

/ t

RECALL

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

DQ (DATA)

6#SSERDDA1#SSERDDA

ADDRESS

SCE

STORE

/ t

RECALL

DATA VALID

HIGH IMPEDANCE

DQ (DATA)

Notes

15.The software sequence is clocked on the falling edge of CE

controlled READs or OE controlled READs.

16.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

Not Recommended for New Designs

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