Cypress Semiconductor Quad HOTLink II CYV15G0404RB Betriebsanweisung Seite 35
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Quad Independent Channel
HOTLink II™ CYV15G0404DXB
Video PHY Demonstration Board
Page 35 of 92
Figure A-5. FPGA for Channel C and D
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
LS7652
Cypress Molson - FPGA2
2
05 12
G. Cosens
Size Drawin g Nu mbe r Revisio n
Date:
Fil e:
Sheet of
Drawn By:FPGA2.Sch Doc
7/ 6/ 2004
B
Linear Systems Ltd.
TXDC[7.. 0]
TXDD [7 . .0]
TXCTC[1..0]
TXCTD[1..0 ]
TXCLKOCTXC L KOD
TXCLKC
TXCLKD
RXDC[7..0]
RXDD[7..0]
RXSTC[2..0]
RXSTD[2..0]
RXCLKC+
RXCLKD+
RXCLKC-
RXCLKD-
SD/HDC
SD/HDD
CD/MUTEC
CD/MUTED
PTXDC[9..0]
PTXDD[9..0]
PRXDC[9 ..0]
PRXDD[9 ..0]
F2DATA0
F2ASDI
F2DC LK
F2nC S
LFIC
LFID
CD/MUTED2
SSI/CDC2
+3.3V +1.5V
DATA
2
DCL K
6
nCS
1
ASDI
5
VCC
8
VCC
7
VCC
3
GND
4
U5
EPCS4SI 8N
+3.3V
1 2
3 4
5 6
7 8
9 10
JP8
HEADER 5X2
+3.3V
F2nCE
F2nCS
F2DCLK
F2CONFI G_ D ON E
F2nC ONFIG
F2DATA0
F2ASDI
F2nC E
F2nC ONFIG
F2CONFI G_ D ON E
F2CONFIG_DONE
F2nC ON FIG
F2DATA0
F2DCLK
F2nC S
F2ASDI
F2DATA0
F2DCLK
F2nC S
F2ASDI
F2nC E F2CONFIG_DONE
F2nC ONFIG
F2nSTATU S
R11
10K
R10
10K
R9
10K
+3.3 V
F2nC E
R12
10K
F2CONFIG_DONE
F2n STATUS
TXCLKC
TXCLKOC
TXDC0
TXDC1
TXDC2
TXDC3
TXDC4
TXDC5
TXDC6
TXDC7
TXCTC0
TXCTC1
TXDC[7.. 0]
TXCTC[ 1.. 0]
RXCLKC+
RXCLKC-
RXDC0
RXDC1
RXDC2
RXDC3
RXDC4
RXDC5
RXDC6
RXDC7
RXSTC0
RXSTC1
RXDC[7..0]
RXSTC[2..0]
PTXDC[9..0]
PRXDC [9..0]
PRXDC0
PRXDC1
PRXDC2
PRXDC3
PRXDC4
PRXDC5
PRXDC6
PRXDC7
PRXDC8
PRXDC9
PTXDC0
PTXDC1
PTXDC2
PTXDC3
PTXDC4
PTXDC5
PTXDC6
PTXDC7
PTXDC8
PTXDC9
TXCLKD
TXCLKOD
TXDD 0
TXDD 1
TXDD 2
TXDD 3
TXDD 4
TXDD 5
TXDD 6
TXDD 7
TXCTD0
TXCTD1
TXDD[7 ..0]
TXCTD[1..0 ]
RXCLKD+
RXCLKD-
RXDD0
RXDD1
RXDD2
RXDD3
RXDD4
RXDD5
RXDD6
RXDD7
RXSTD0
RXSTD 1
RXDD[7..0]
RXSTD[2 .. 0]
PTX DD[9..0]
PRXDD[9 ..0]
PTXDD0
PTXDD1
PTXDD2
PTXDD3
PTXDD4
PTXDD5
PTXDD6
PTXDD7
PTXDD8
PTXDD9
PRXDD0
PRXDD1
PRXDD2
PRXDD3
PRXDD4
PRXDD5
PRXDD6
PRXDD7
PRXDD8
PRXDD9
C33
0.1 u
C34
0.1 u
C23
0.1 u
C24
0.1 u
C25
0.1 u
C26
0.1 u
C27
0.1 u
C28
0.1 u
C29
0.1 u
C30
0.1 u
C31
0.1 u
C32
0.1 u
+3.3V +1.5V
C22
0.1 u
+3.3V
RXSTC2
RXSTD2
RCLKE NC
RCLKE ND
SPDSELC
SPDSELD
1
2
3
JB3
3PIN
1
2
3
JB4
3PIN
R7
0
R8
0
+3.3V
+3.3V
SPDSELC'
SPDSE LD'
PTXCLKC
PRXCLKC
PTXCLKD
PRXCLKD
inseld
T16
txdc[4 ]
T17
ul cd
R17
spdseld
R18
RESERVED_INPUT
R15
ul cc
R16
lpend
P16
txdc[0 ]
P17
inselc
P15
RESERVED_INPUT
P14
RESERVED_INPUT
N14
sd_hdc
N18
cd_mu tec
N17
RESERVED_INPUT
N13
RESERVED_INPUT
N12
RESERVED_INPUT
N16
RESERVED_INPUT
N15
cd_mu ted
M1 8
ssi_cdc2
M1 7
fcl kc_ p
K16
fcl kc_ n
K15
CONF_DONE
K17
nSTATUS
L12
TCK
K18
TMS
K14
TDO
K13
GNDG_ PLL2
J18
GNDA_ PLL2
K12
txclkoc
J16
rxclkc_p
J15
VCCA_PLL2
J12
TDI
J17
rxclkc_n
J14
RESERVED_INPUT
G13
RESERVED_INPUT
G14
RESERVED_INPUT
G15
led2 70c
G16
RESERVED_INPUT
G12
RESERVED_INPUT
F12
led5 40d
F18
led3 60d
F17
RESERVED_INPUT
F13
RESERVED_INPUT
F14
led7 425d
F16
RESERVED_INPUT
F15
led2 70d
E17
ledlfid
E16
RESERVED_INPUT
E15
pt xdc[9]
D18
RESERVED_INPUT
E14
ledc dd
D16
prxdd[9]
D15
led2
C17
pt xdc[8]
D17
BANK3
RESERVED_INPUT
M1 4
RESERVED_INPUT
M1 5
RESERVED_INPUT
M1 6
cd_mu ted2
L18
sd_hdd
L17
RESERVED_INPUT
M1 3
RESERVED_INPUT
L13
RESERVED_INPUT
L16
RESERVED_INPUT
L15
RESERVED_INPUT
L14
RESERVED_INPUT
J13
RESERVED_INPUT
H13
RESERVED_INPUT
H14
RESERVED_INPUT
H15
led7 425c
H16
led3 60c
H17
led5 40c
H18
ledlfic
G18
ledc dc
G17
U3C
EP1C20F324C8
txct d[ 0]
U3
txcl kd
V4
VCCINT
M8
GND
N8
rxdc[0]
T4
rxdd[0]
U4
rxstd[1]
T5
txd d[7]
U5
RES ERVED_INPUT
R4
rxdc[1]
R5
txd d[6]
V6
txd d[5]
U6
RES ERVED_INPUT
P6
RES ERVED_INPUT
P7
rxdd[5]
T6
txd d[3]
U7
txd d[4]
V7
RES ERVED_INPUT
T7
rxdc[5]
R7
txd d[0]
U8
txd d[1]
V8
RES ERVED_INPUT
T8
RES ERVED_INPUT
P9
rxdd[3]
T10
rxdc[3]
R10
lfi c
R11
rxdd[2]
T11
RES ERVED_INPUT
U11
txct c[0]
V11
GND
N10
VCCINT
M1 0
RES ERVED_INPUT
P12
RES ERVED_INPUT
P13
txd c[1 ]
U14
lfi d
T14
rxdc[6]
R14
spdselc
V15
rcl kend
U15
VCCINT
N11
GND
M1 1
txd c[7 ]
U16
lp en c
T15
BANK4
rxstc[0]
R6
txerrc
U9
txd d[2]
V9
rcl kenc
R9
rxdd[4]
T9
GND
M9
VCCINT
N9
txd c[6 ]
U10
txcl kc
V10
RES ERVED_INPUT
P10
txd c[3 ]
V12
txd c[2 ]
U12
rxdd[6]
T12
rxdc[2]
R12
txd c[5 ]
V13
txct c[1]
U13
rxdd[7]
T13
rxdc[7]
R13
rxdc[4]
R8
U3D
EP1C20F32 4C 8
fd [ 1]
C3
fd [ 2]
C2
fd [ 3]
D3
fd[ 13]
D2
rdy[ 1]
D4
fd[ 12]
D1
fd [ 4]
E3
fd [ 5]
E2
fd[ 10]
F1
RESERVED_INPUT
E4
RESERVED_INPUT
E5
fd[ 11]
F2
fd [ 6]
F3
fd [ 7]
F4
RESERVED_INPUT
F5
fd [ 8]
G1
fd [ 9]
G2
RESERVED_INPUT
F6
RESERVED_INPUT
F7
RESERVED_INPUT
H6
RESERVED_INPUT
J1
DATA0
H7
nCONFIG
J2
VCCA_PLL1
J5
rxclkd_ p
J3
txcl kod
J4
GNDA_ PLL1
K1
GNDG_ PLL1
J6
nCEO
K2
nCE
J7
MSEL 0
K3
MSEL 1
K7
DCL K
L1
RESERVED_INPUT
K6
fclkd_p
K4
fclkd_n
K5
RESERVED_INPUT
M4
RESERVED_INPUT
N1
RESERVED_INPUT
N2
RESERVED_INPUT
M6
RESERVED_INPUT
N7
RESERVED_INPUT
N5
RESERVED_INPUT
N6
RESERVED_INPUT
N3
RESERVED_INPUT
N4
RESERVED_INPUT
P5
RESERVED_INPUT
P2
rxstd[2]
P3
txerrd
R1
rxstc[2]
P4
rxdd[ 1]
R2
rxstc[1]
R3
txct d[ 1]
T2
rxstd[0]
T3
BANK1
ctl[0]
G3
ctl[1]
G4
RESERVED_INPUT
G5
RESERVED_INPUT
G6
pa7_ fl agd_ slcs
H1
reset_n
H2
ctl[2]
H3
rxclkd_ n
H4
RESERVED_INPUT
H5
RESERVED_INPUT
L7
RESERVED_INPUT
L6
sdi
L2
scse1
L3
RESERVED_INPUT
L5
RESERVED_INPUT
L4
sdo
M1
RESERVED_INPUT
M3
scl
M2
RESERVED_INPUT
M5
U3A
EP1C20F32 4C8
prxdc[ 9]
C16
prxdc[ 8]
B16
VCCINT
G11
GND
F11
prxdc[ 7]
B15
ptxdc [ 7]
A15
ptxdd[ 9]
C15
prxdd [8 ]
D14
prxdc[ 6]
B14
ptxdd[ 8]
C14
RESE RVE D _INPUT
E13
GND
G10
VCCINT
F10
ptxdd[ 5]
C11
prxdd [5 ]
D11
prxdc[ 3]
B11
ptxdc [ 4]
A11
ptxdd[ 4]
C10
prxdd [4 ]
D10
RESE RVE D _INPUT
E10
ptxdd[ 2]
C8
ptxdc [ 1]
A8
prxdc[ 0]
B8
RESE RVE D _INPUT
E8
RESE RVE D _INPUT
E7
ptxdc [ 0]
A7
prxclkc
B7
ptxdd[ 1]
C7
RESE RVE D _INPUT
E6
prxdd [0 ]
D6
clkout
B6
ptxdd[ 0]
C6
ptxcl kc
A6
ifcl k
B5
ptxcl kd
C5
prxclkd
D5
fd [ 15 ]
A4
fd [ 14 ]
B4
VCCINT
F8
GND
G8
fd [ 0]
B3
rdy[0]
C4
BANK2
prxdc[ 5]
B13
ptxdc [ 6]
A13
prxdd [7 ]
D13
ptxdd[ 7]
C13
prxdd [6 ]
D12
ptxdd[ 6]
C12
prxdc[ 4]
B12
ptxdc [ 5]
A12
prxdc[ 2]
B10
ptxdc [ 3]
A10
VCCINT
G9
GND
F9
prxdd [3 ]
D9
ptxdd[ 3]
C9
ptxdc [ 2]
A9
prxdc[ 1]
B9
prxdd [2 ]
D8
prxdd [1 ]
D7
RESE RVE D _INPUT
E11
U3B
EP1C20F32 4C 8
VC CI NT
A17
VC CI NT
A2
VC CI NT
B1
VC CI NT
B18
VC CI NT
H10
VC CI NT
J9
VC CI NT
K10
VC CI NT
L9
VC CI NT
U1
VC CI NT
U18
VC CI NT
V17
VC CI NT
V2
VC C I O1
E1
VC C I O1
G7
VC C I O1
M7
VC C I O1
P1
VC C I O2
A14
VC C I O2
A5
VC C I O2
E12
VC C I O2
E9
VC C I O3
E18
VC C I O3
H12
VC C I O3
M12
VC C I O3
P18
VC C I O4
P11
VC C I O4
P8
VC C I O4
V14
VC C I O4
V5
GN D
A1
GN D
A1 6
GN D
A1 8
GN D
A3
GN D
B17
GN D
B2
GN D
C1
GN D
C18
GN D
H1 1
GN D
H8
GN D
H9
GN D
J10
GN D
J11
GN D
J8
GN D
K1 1
GN D
K8
GN D
K9
GN D
L10
GN D
L11
GN D
L8
GN D
T1
GN D
T18
GN D
U1 7
GN D
U2
GN D
V1
GN D
V1 6
GN D
V1 8
GN D
V3
POWER/GND
U3E
EP1C20F32 4C 8
SPDSELD'
SPDSELC'
LPENC
LPEND
INSELC
INSELD
ULC C
ULC D
SDI
SDO
SCL
SCSE1
F2nC S
F2DATA0
F2nC ONFIG
F2DCLK
F2ASDI
F2nC E
RESET#
TC K
TDI
TM S
TDO
+1.5V
+1.5V
+1.5VA
C152
0.1 u
C153
1n
+1.5VA
C150
0.1 u
C151
1n
C157
0.1 u
C156
0.1 u
FD[15..0 ]
CTL[2..0]
RDY[1.. 0]
FD[15..0 ]
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
FD10
FD11
FD12
FD13
FD1 4
FD1 5
CTL[2..0] CTL0
CTL1
CTL2
RDY[1.. 0] RDY0
RDY1
CL KO UT
IF C L K
PA7/*FLAGD /SLCS#
D23
LED2
D24
LED2
D25
LED2
D26
LED2
D21
LED2
D22
LED2
D17
LED2
D18
LED2
D19
LED2
D20
LED2
D15
LED2
D16
LED2
R186
22 1
R187
22 1
R188
22 1
R189
22 1
R190
22 1
R191
22 1
R180
22 1
R181
22 1
R182
22 1
R183
22 1
R184
22 1
R185
22 1
LFIC
CDC
L27 0C
L36 0C
L54 0C
L74 25C
LFID
CDD
L27 0D
L36 0D
L54 0D
L74 25D
LFIC
CDC
L270C
L360C
L540C
L74 25C
LFID
CDD
L270D
L360D
L540D
L74 25D
D31
LED2
R197
221
+3.3V
C186
0.1 u
C187
0.1 u
C188
0.1 u
C189
0.1 u
C190
0.1 u
C191
0.1 u
C192
0.1 u
C193
0.1 u
C194
0.1 u
C195
0.1 u
C196
0.1 u
C197
0.1 u
+3.3V +1.5V
C185
0.1 u
C184
0.1 u
TXERRC
TXERRD
FCLKD+
FCLKD-
FCLKC +
FCLKC -
R215
0
R216
0
+
C251
10 u
+3.3V
[+] Feedback
- Quad Independent Channel 1
- HOTLink II™ CYV15G0404DXB 1
- Video PHY Demonstration Board 1
- Users Guide 1
- Page 2 of 92 2
- Page 3 of 92 3
- LIST OF TABLES 4
- 1.0 Introduction 5
- 2.0 Kit Contents 5
- 3.0 Demo Board Features 6
- 4.0 Board Architecture 7
- 4.2 Clocking Architecture 8
- Programmable 10
- 4.4 Power Supply 11
- 5.0 GUI and Operating Modes 12
- [+] Feedback 13
- 5.1 Setting the SDI Data Rate 14
- 5.3 Standard 15
- 5.4 Transmit Test Pattern 16
- 5.5 Status 16
- 6.0 Sample Test Procedures 17
- 6.3 Tests 19
- Page 23 of 92 23
- Page 24 of 92 24
- Page 27 of 92 27
- Page 28 of 92 28
- 7.0 Summary 29
- 8.0 References 29
- Linear Syst ems Ltd 33
- Page 36 of 92 36
- Page 38 of 92 38
- (GERBER Files) 43
- Page 45 of 92 45
- Figure B-2. Top Overlay 45
- Page 64 of 92 64
- (Drill and Assembly) 65
- Page 66 of 92 66
- Figure C-1. Drill Placement 66
- Page 67 of 92 67
- Figure C-2. Assembly–Top View 67
- Page 68 of 92 68
- Video Demo Board 69
- Setting Configurations 85
- SD-SDI to HD-SDI Upconversion 86
- Channel B 87
- Channel A 87
- FPGA (U2) 87
- Board Modification 88
- FPGA(U2) 89
- PLL 1 PLL 2 JP11 89
- Page 91 of 92 91
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