Cypress Semiconductor CY7C1399B Bedienungsanleitung PDF herunterladen (Seite 13)

AN57322

November 4, 2009 Document No. 001-57322 Rev. ** 13

if( GPIFTRIG & 0x80 )

// if GPIF interface IDLE

{

if ( ! (

EP24FIFOFLGS & 0x02 ) ) // if there's a

packet in the peripheral domain for EP2

{

if(enum_high_speed)

// if the FX2 enumerated at high-speed

{

if ( len >

0x0200 ) // if the transfer length

is greater than 512 bytes,

{

GPIFTCB1 = 0x02; // set GPIF transaction

count to 512, since

//GPIFADR

can only access 512 locations at a time

SYNCDELAY;

GPIFTCB0 = 0x00;

SYNCDELAY;

Tcount = 0x0200;

}

else

{

GPIFTCB1 = EP2FIFOBCH; // else set

GPIF transaction count to EP2

//FIFO byte count

SYNCDELAY;

GPIFTCB0 =

EP2FIFOBCL;

SYNCDELAY;

Tcount = len;

}

}

else

// if the FX2 enumerated at full-speed

{

if ( len > 0x040 )

// if the transfer length is greater than

64 bytes,

{

GPIFTCB1 = 0x00; // set GPIF

transaction count to 64

SYNCDELAY;

GPIFTCB0

= 0x40;

SYNCDELAY;

Tcount =

0x0040;

}

else

{

GPIFTCB1 = EP2FIFOBCH;

SYNCDELAY;

GPIFTCB0

= EP2FIFOBCL;

SYNCDELAY;

Tcount =

len;

}

}

GPIFTRIG

= GPIF_EP2; // launch GPIF FIFO WRITE

Transaction from EP2 FIFO

SYNCDELAY;

while( !(

GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7

GPIF Done bit

{

;

}

SYNCDELAY;

len = len - Tcount;

// decrement transfer length by Tcount

if (!(len % 0x0200))

// if the transfer length is not a modulus

of 512, no need to

{

// reset GPIFADR[8:0] to access next bank

of 512 bytes,

//

handles full-speed case and high-speed case

GPIFADRH = 0x00;

// reset GPIFADR[8:0] to access the next

bank at offset 0

GPIFADRL = 0x00;

IOA = ( ( ( IOA >> 4 ) + 1 ) << 4 );

// increment the bank address by 1 to

access

//next bank of 512

}

}

}

}

EP0BCH = 0;

EP0BCL = 1;

EP0CS |= bmHSNAK;

break;

}

case VX_BC: // actuate read from SRAM

{

EP0BUF[0] = VX_BC;

IOA = (IOA & 0x0F) + (SETUPDAT[3]

<< 3); // select bank of 16x512 (bit

shift MSB of wValue by 3

// and OR it with

PA[7:4]

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