AN57322
November 4, 2009 Document No. 001-57322 Rev. ** 4
tWC (Write Cycle Time) (min)
When IFCLK=48 MHz, each GPIF cycle is 20.83 ns. Therefore, it
only takes one cycle to write a byte.
tPWE (WE/ Pulse Width) (min)
When IFCLK=48 MHz, each GPIF cycle is 20.83 ns. Therefore,
WE/ only needs to be driven low for one cycle.
tSD (Data Setup to Write End) (min)
Driving data together with WE/ LOW meets the setup time easily.
tHA (Address Hold from Write End) (min)
It is not required to keep the address asserted after WE/ goes
HIGH.
tSA (Address Set-Up to Write Start) (min)
No setup time required for address with respect to WE/ going LOW.
This means that Address and WE/ can be asserted at the same
time.
tAW (Address Set-Up to Write End) (min)
Because address is asserted for one GPIF cycle and WE/ is de-
asserted in the next cycle, this setup time is easily met.
tHD (Data Hold from Write End) (min)
It is not required to keep driving data after WE/ is de-asserted.
Now that the timing parameters involved are understood,
the write waveform can be designed in GPIF designer.
The following state flow diagram must be accomplished:
Follow these steps to complete the FIFO Write
waveform
1. Click the FIFO Write waveform tab.
2. Click on the WE/ trace one clock cycle from the left
boundary. This places an action point and creates the
WE/ waveform. State 0 (s0) is generated
automatically and lasts for 1 IFCLK cycle (20.83 ns).
WE/ is asserted for 20.83 ns. This easily satisfies the
tPWE requirement.
3. Assert and de-assert CE/ along with WE/. To do this,
click on the CE/ trace one clock cycle from the left
boundary.
4. OE/ must be HIGH throughout the waveform. To
ensure this, right-click on the action point on the OE/
trace and select High (1). This considers the CTL line
activity and the waveform appears as shown in the
following diagram.
5. The data bus is also driven in s0. To do this, right-
click on the data action point, and select Activate
Data.
6. The data bus should only be driven for one clock
cycle. To stop driving the data after one clock cycle,
place another action point on the data trace after one
clock cycle. Notice that the data trace is high for just
the duration of s0 now. The waveform should appear
as follows.
7. The next step is to add a decision point (DP) state to
loop through this waveform until the GPIF transaction
count (GPIFTC) expires. To do this, test the internal
TCXpire flag in a DP state and only branch to the
IDLE state when the transaction count expires. In the
DP state, the GPIFADR lines are also incremented.
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