Cypress Semiconductor CY7C1399B Bedienungsanleitung PDF herunterladen (Seite 3)

AN57322

November 4, 2009 Document No. 001-57322 Rev. ** 3

The window appears as follows. Click OK.

9. Right-click on the ‟48 MHz CLK‟. Uncheck IFCLK

Output. The Clock Properties window is displayed.

The interface is asynchronous and GPIF uses the

internal 48 MHz clock.

These steps define and configure the GPIF interface for

the SRAM. The next step is to design the read and write

waveforms.

GPIF Waveforms

When the interface is configured, create the read and write

waveforms using which communication takes place over

the interface.

Write Waveform

Write waveforms are designed to write data from the

Endpoint FIFO into the SRAM. They must satisfy the

timing requirements of the various signals involved in the

write cycle of the SRAM.

In the GPIF Designer window, click the Single Read tab to

select it. Right-click and select Set Tab Label; rename as

“Unused”. Repeat with “Single Write” tab, also renaming it

as “Unused”.

Select Tools > Map Waveforms to WFSELECT.

Make sure that the FIFO Write waveform is mapped to

FIFOWR and the FIFO Read waveform is mapped to

FIFORD. This ensures that when GPIF FIFO Write

operation is launched, the FIFO Write waveform is

executed and when a GPIF FIFO Read operation is

launched, the FIFO Read waveform is executed. The

mapping of bit fields is identical to the bit fields in the

GPIFWSELECT register. The waveforms are already

mapped appropriately; click OK.

To construct the FIFO Write waveform, first review the

write cycle timing for the SRAM and its timing parameters.

Figure 2. Write Cycle Timing for SRAM

GPIFADR[8:0]

CTL0

CTL2

CTL1

PB[7:0]

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Cypress Semiconductor CY7C1399B Bedienungsanleitung Seite 3