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CYDC128B16

Document #: 001-01638 Rev. *H Page 21 of 29

Figure 8. Semaphore Read After Write Timing, Either Side

[19, 20]

Figure 9. Timing Diagram of Semaphore Contention

[21, 22]

Notes

19. If the CE

or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

20. CE

= HIGH for the duration of the above timing (both write and read cycle).

21. I/O

= I/O

= LOW (request semaphore); CE

= CE

= HIGH.

22. If t

SPS

is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.

Switching Waveforms (continued)

SOP

SAA

VALID ADRESS VALID ADRESS

DATA

VALID

OHA

ACE

SOP

SCE

PWE

SWRD

DOE

WRITE CYCLE READ CYCLE

R/W

I/O

SEM

–A

DATA

OUT

VALID

MATCH

SPS

MATCH

R/W

SEM

R/W

SEM

–A

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